LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 221

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
Fig 33. Format and states in the Slave Transmitter mode
12.11.5.1 I2STAT = 0xF8
12.11.5.2 I2STAT = 0x00
reception of the own
Slave address and
one or more Data
bytes all are
acknowledged
last data byte
transmitted. Switched
to Not Addressed
Slave (AA bit in
I2CON = “0”)
12.11.5 Miscellaneous states
arbitration lost as
Master and
addressed as Slave
DATA
n
There are two I2STAT codes that do not correspond to a defined I
Table
This status code indicates that no relevant information is available because the serial
interrupt flag, SI, is not yet set. This occurs between other states and when the I
is not involved in a serial transfer.
This status code indicates that a bus error has occurred during an I
bus error is caused when a START or STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I
set. To recover from a bus error, the STO flag must be set and SI must be cleared. This
A
232). These are discussed below.
S
from Master to Slave
from Slave to Master
any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I
2
C bus
SLA
All information provided in this document is subject to legal disclaimers.
R
Rev. 2 — 7 July 2010
A8H
B0H
A
A
DATA
B8H
2
A
C block signals. When a bus error occurs, SI is
Chapter 12: LPC13xx I2C-bus controller
DATA
C8H
C0H
A
A
P OR S
ALL ONES
2
C hardware state (see
2
C serial transfer. A
UM10375
© NXP B.V. 2010. All rights reserved.
P OR S
2
C block
223 of 333