LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 3

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

1.1 Introduction
1.2 How to read this manual
1.3 Features
UM10375
User manual
The LPC13xx are ARM Cortex-M3 based microcontrollers for embedded applications
featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC13xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC13xx series includes up to 32 kB of flash memory,
up to 8 kB of data memory, USB Device, one Fast-mode Plus (FM+) I
UART, four general purpose timers, and up to 42 general purpose I/O pins.
This user manual describes parts LPC1311, LPC1313, LPC1342, LPC1343. Part-specific
features and registers are listed at the beginning of each chapter.
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UM10375
Chapter 1: LPC13xx Introductory information
Rev. 2 — 7 July 2010
ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug and Serial Wire Trace port.
32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming
memory.
8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Code Read Protection (CRP) with different security levels.
Selectable boot-up: UART or USB (USB on LPC134x only).
On-chip drivers for MSC and HID (LPC134x only).
Serial interfaces:
– USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43
– UART with fractional baud rate generation, modem, internal FIFO, and
– SSP controller with FIFO and multi-protocol capabilities.
– I
only).
RS-485/EIA-485 support.
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
2
C-bus interface supporting full I
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
2
C-bus specification and Fast-mode Plus with a
2
C interface, one
© NXP B.V. 2010. All rights reserved.
User manual
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