LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 51

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
4.3 Functional description
UM10375
User manual
4.2.2 General purpose registers 0 to 3
4.2.3 General purpose register 4
Table 58.
The general purpose registers retain data through the Deep power-down mode when
power is still applied to the V
Only a “cold” boot when all power has been completely removed from the chip will reset
the general purpose registers.
Table 59.
The general purpose register 4 retains data through the Deep power-down mode when
power is still applied to the V
Only a “cold” boot, when all power has been completely removed from the chip, will reset
the general purpose registers.
The hysteresis of the WAKEUP pin in Deep power-down mode can be controlled by bit 10
of this register.
Remark: If there is a possibility that the external voltage applied on pin V
2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be
disabled in this register before entering Deep power-down mode in order for the chip to
wake up.
Table 60.
See
Bit
11
31:12
Bit
31:0
Bit
9:0
10
31:11
Section 3.8
Symbol
DPDFLAG
-
Symbol
-
WAKEUPHYS
GPDATA
Symbol
GPDATA
General purpose registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to
0x4003 8010) bit description
General purpose register 4 (GPREG4, address 0x4003 8014) bit description
Power control register (PCON, address 0x4003 8000) bit description
All information provided in this document is subject to legal disclaimers.
for details on power management and the Deep power-down mode.
Value
0
1
-
Rev. 2 — 7 July 2010
Value
-
1
0
Description
Data retained during Deep power-down mode.
DD
DD
Description
Deep power-down flag
Read: Deep power-down mode not entered.
Write: No effect.
Read: Deep power-down mode entered.
Write: Clear the Deep power-down flag.
Reserved. Do not write ones to this bit.
pin but the chip has entered Deep power-down mode.
pin but the chip has entered Deep power-down mode.
Description
Reserved. Do not write ones to this bit.
WAKEUP pin hysteresis enable
Hysteresis for WAKEUP pin enabled.
Hysteresis for WAKUP pin disabled.
Data retained during Deep power-down mode.
Chapter 4: LPC13xx Power Management Unit (PMU)
UM10375
© NXP B.V. 2010. All rights reserved.
DD
drops below
…continued
Reset
value
0x0
52 of 333
Reset
value
0x0
0x0
0x0
0x0
Reset
value
0x0
0x0
0x0