LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 322

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 279: A/D Control Register (AD0CR - address
Table 280: A/D Global Data Register (AD0GDR - address
Table 281: A/D Status Register (AD0STAT - address
Table 282: A/D Interrupt Enable Register (AD0INTEN -
Table 283: A/D Data Registers (AD0DR0 to AD0DR7 -
Table 284. LPC13xx flash configurations . . . . . . . . . . . .290
Table 285. Bootloader versions . . . . . . . . . . . . . . . . . . . .290
Table 286. CRP levels for USB boot images . . . . . . . . . .295
Table 287. LPC13xx flash sectors . . . . . . . . . . . . . . . . . .297
Table 288. Code Read Protection (CRP) options . . . . . .298
Table 289. Code Read Protection hardware/software
Table 290. ISP commands allowed for different CRP
Table 291. ISP command summary. . . . . . . . . . . . . . . . .300
Table 292. ISP Unlock command . . . . . . . . . . . . . . . . . .300
Table 293. ISP Set Baud Rate command . . . . . . . . . . . .301
Table 294. ISP Echo command . . . . . . . . . . . . . . . . . . . .301
Table 295. ISP Write to RAM command . . . . . . . . . . . . .302
Table 296. ISP Read Memory command. . . . . . . . . . . . .302
Table 297. ISP Prepare sector(s) for write operation
Table 298. ISP Copy command . . . . . . . . . . . . . . . . . . . .303
Table 299. ISP Go command. . . . . . . . . . . . . . . . . . . . . .304
Table 300. ISP Erase sector command . . . . . . . . . . . . . .304
Table 301. ISP Blank check sector command . . . . . . . . .305
Table 302. ISP Read Part Identification command . . . . .305
Table 303. LPC13xx part identification numbers . . . . . . .305
Table 304. ISP Read Boot Code version number
Table 305. ISP Compare command. . . . . . . . . . . . . . . . .306
Table 306. ReadUID command . . . . . . . . . . . . . . . . . . . .306
Table 307. ISP Return Codes Summary . . . . . . . . . . . . .306
Table 308. IAP Command Summary . . . . . . . . . . . . . . . .308
Table 309. IAP Prepare sector(s) for write operation
Table 310. IAP Copy RAM to flash command . . . . . . . . .310
Table 311. IAP Erase Sector(s) command. . . . . . . . . . . .310
Table 312. IAP Blank check sector(s) command . . . . . . . 311
Table 313. IAP Read Part Identification command . . . . . 311
Table 314. IAP Read Boot Code version number
Table 315. IAP Compare command. . . . . . . . . . . . . . . . .312
Table 316. Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . .312
Table 317. IAP ReadUID command. . . . . . . . . . . . . . . . .312
Table 318. IAP Status Codes Summary . . . . . . . . . . . . .313
Table 319. Memory mapping in debug mode . . . . . . . . .313
Table 320. Flash configuration register (FLASHCFG,
Table 321. Serial Wire Debug pin description . . . . . . . . .316
Table 322. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .317
UM10375
User manual
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
0x4001 C000) bit description . . . . . . . . . . . . .286
0x4001 C004) bit description . . . . . . . . . . . . .287
0x4001 C030) bit description . . . . . . . . . . . . .288
address 0x4001 C00C) bit description . . . . . .288
addresses 0x4001 C010 to 0x4001 C02C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .289
interaction . . . . . . . . . . . . . . . . . . . . . . . . . . .298
levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
address 0x4003 C010) bit description . . . . . .314
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 21: LPC13xx Supplementary information
UM10375
© NXP B.V. 2010. All rights reserved.
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