LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 18

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
3.5.7 System oscillator control register
3.5.8 Watchdog oscillator control register
This register configures the frequency range for the system oscillator.
Table 12.
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk =
Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ± 40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the IRC or system clock.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
Table 13.
Bit
0
1
31:2
Bit
4:0
Symbol
BYPASS
FREQRANGE
-
Symbol
DIVSEL
description
Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
Fclkana
All information provided in this document is subject to legal disclaimers.
Value
00000 2 × (1 + DIVSEL) = 2
00001 2 × (1 + DIVSEL) = 4
00010 2 × (1 + DIVSEL) = 6
...
11111
⁄
(2 × (1 + DIVSEL))
Rev. 2 — 7 July 2010
Description
Select divider for Fclkana.
wdt_osc_clk =
...
2 × (1 + DIVSEL) = 64
Value
0
1
0
1
-
Description
Bypass system oscillator
Oscillator is not bypassed.
Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN and XTALOUT pins.
Determines frequency range for Low-power
oscillator.
1 - 20 MHz frequency range.
15 - 25 MHz frequency range
Reserved
= 7.8 kHz to 1.7 MHz (nominal values).
Fclkana
Chapter 3: LPC13xx System configuration
⁄
(2 × (1 + DIVSEL))
.
UM10375
© NXP B.V. 2010. All rights reserved.
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Reset
value
0x0
0x0
0x00
Reset
value
0x0