LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet
LPC1313FBD48,151
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UM10375 LPC1311/13/42/43 User manual Rev. 2 — 7 July 2010 Document information Info Content Keywords ARM Cortex-M3, microcontroller, USB, LPC1311, LPC1313, LPC1342, LPC1343 Abstract LPC1311/13/42/43 user manual User manual ...
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... NXP Semiconductors Revision history Rev Date Description 2 20100707 LPC1311/13/42/43 user manual Modifications: • • • • • • • • • • • • • • • • • • • • • • • • • 1 20091106 LPC1311/13/42/43 user manual ...
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UM10375 Chapter 1: LPC13xx Introductory information Rev. 2 — 7 July 2010 1.1 Introduction The LPC13xx are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex- next ...
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... NXP Semiconductors • Other peripherals: – General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. – GPIO pins can be used as edge and level sensitive interrupt sources. – High-current output driver (20 mA) on one pin. – High-current sink drivers (20 mA) on two I – Four general purpose counter/timers with a total of four capture inputs and 13 match outputs. – ...
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... NXP Semiconductors 1.4 Ordering options Table 1. Ordering options for the LPC13xx parts Type number Flash Total SRAM LPC1311FHN33 LPC1313FBD48 LPC1313FHN33 LPC1342FHN33 LPC1343FBD48 LPC1343FHN33 UM10375 User manual Chapter 1: LPC13xx Introductory information 2 USB UART I C/ RS-485 Fast Device 1 1 Device 1 1 Device 1 1 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 1.5 Block diagram TEST/DEBUG CORTEX-M3 I-code bus HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (2) DTR, DSR , CTS, (2) (2) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 (1) LPC1342/43 only. (2) LQFP48 package only. ...
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UM10375 Chapter 2: LPC13xx Memory mapping Rev. 2 — 7 July 2010 2.1 How to read this chapter See Table 2 Table 2. Part LPC1311 LPC1313 LPC1342 LPC1343 2.2 Memory map Figure 2 shows the memory and peripheral address space ...
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... NXP Semiconductors LPC1311/13/42/ reserved AHB peripherals reserved APB peripherals 1 GB reserved AHB SRAM bit-band alias addressing reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC1313/1343) I-code/D-code memory space 4 kB SRAM (LPC1311/1342) reserved 32 kB on-chip flash (LPC1313/43 on-chip flash (LPC1342 on-chip flash (LPC1311 Fig 2 ...
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UM10375 Chapter 3: LPC13xx System configuration Rev. 2 — 7 July 2010 3.1 How to read this chapter The system configuration registers apply to all LPC13xx parts with the following exceptions: Input pins to the start logic For HVQFN packages, ...
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... NXP Semiconductors 3.2 Introduction The system configuration block controls oscillators, the power management unit, and clock generation of the LPC13xx. Also included in this block are registers for setting the priority for AHB access and a register for remapping flash, SRAM, and ROM memory areas ...
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... NXP Semiconductors 3.4 Clocking and power control See Figure 3 The LPC131x include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. ...
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... NXP Semiconductors irc_osc_clk wdt_osc_clk MAINCLKSEL sys_pllclkout irc_osc_clk SYS PLL sys_osc_clk sys_pllclkin SYSPLLCLKSEL sys_osc_clk USB PLL usb_pllclkin USBPLLCLKSEL USB is available in parts LPC134x only. Fig 3. LPC13xx CGU block diagram 3.5 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function ...
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... NXP Semiconductors Table 5. Register overview: system control block (base address 0x4004 8000) Name Access Address offset Description SYSMEMREMAP R/W 0x000 PRESETCTRL R/W 0x004 SYSPLLCTRL R/W 0x008 SYSPLLSTAT R 0x00C USBPLLCTRL R/W 0x010 USBPLLSTAT R 0x014 - - 0x018 - 0x01C SYSOSCCTRL R/W 0x020 WDTOSCCTRL R/W 0x024 ...
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... NXP Semiconductors Table 5. Register overview: system control block (base address 0x4004 8000) Name Access Address offset Description - - 0x0EC - 0x0FC PIOPORCAP0 R 0x100 PIOPORCAP1 R 0x104 - - 0x108 - 0x14C BODCTRL R/W 0x150 - - 0x154 SYSTCKCAL R/W 0x158 - - 0x15C - 0x1FC STARTAPRP0 R/W 0x200 STARTERP0 R/W 0x204 STARTRSRP0CLR ...
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... NXP Semiconductors Table 6. Bit Symbol 1:0 MAP 31:2 - 3.5.2 Peripheral reset control register This register allows software to reset the SSP and I2C peripherals. Writing the SSP_RST_N or I2C_RST_N bits resets the SSP or I2C peripheral. Writing a 1 de-asserts the reset. Remark: Before accessing the SSP and I2C peripherals, write this register to ensure that the reset signals to the SSP and I2C are de-asserted ...
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... NXP Semiconductors Table 8. Bit Symbol 4:0 MSEL 6:5 PSEL 31:7 - 3.5.4 System PLL status register This register is a Read-only register and supplies the PLL lock status (see Section 3.10.1). Table 9. Bit Symbol 0 LOCK 31:1 - 3.5.5 USB PLL control register The USB PLL is identical to the system PLL and is used to provide a dedicated clock to ...
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... NXP Semiconductors Table 10. Bit Symbol 6:5 PSEL 31:7 - 3.5.6 USB PLL status register This register is a Read-only register and supplies the PLL lock status (see Section 3.10.1). Table 11. Bit Symbol 0 LOCK 31:1 - UM10375 User manual USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description ...
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... NXP Semiconductors 3.5.7 System oscillator control register This register configures the frequency range for the system oscillator. Table 12. Bit Symbol 0 BYPASS 1 FREQRANGE 31:2 - 3.5.8 Watchdog oscillator control register This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana) ...
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... NXP Semiconductors Table 13. Bit Symbol 8:5 FREQSEL 31:9 - 3.5.9 Internal resonant crystal control register This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up. Table 14. Bit Symbol 7:0 TRIM 31:8 - UM10375 User manual ...
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... NXP Semiconductors 3.5.10 System reset status register The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register, but if another reset signal (e.g., EXTRST) remains asserted after the POR signal is negated, then its bit is set to detected ...
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... NXP Semiconductors Table 16. Bit Symbol 1:0 SEL 31:2 - 3.5.12 System PLL clock source update enable register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN ...
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... NXP Semiconductors 3.5.14 USB PLL clock source update enable register This register updates the clock source of the USB PLL with the new input clock after the USBPLLCLKSEL register has been written to. In order for the update to take effect at the USB PLL input, first write a zero to the USBPLLUEN register and then write a one to USBPLLUEN ...
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... NXP Semiconductors Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 21. Bit Symbol 0 ENA 31:1 - 3.5.17 System AHB clock divider register This register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV bits to 0x0 ...
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... NXP Semiconductors Table 23. Bit Symbol 2 RAM 3 FLASHREG 4 FLASHARRAY 5 I2C 6 GPIO 7 CT16B0 8 CT16B1 9 CT32B0 10 CT32B1 11 SSP 12 UART 13 ADC UM10375 User manual System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Value Description Enables clock for RAM. 0 Disabled 1 Enabled Enables clock for flash register interface. ...
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... NXP Semiconductors Table 23. Bit Symbol 14 USB_REG 15 WDT 16 IOCON 31:17 - 3.5.19 SSP clock divider register This register configures the SSP peripheral clock SSP_PCLK. The SSP_PCLK can be shut down by setting the DIV bits to 0x0. Table 24. Bit Symbol 7:0 DIV 31:8 - 3.5.20 UART clock divider register This register configures the UART peripheral clock UART_PCLK ...
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... NXP Semiconductors 3.5.21 Trace clock divider register This register configures the ARM trace clock. The trace clock can be shut down by setting the DIV bits to 0x0. Table 26. Bit Symbol 7:0 DIV 31:8 - 3.5.22 SYSTICK clock divider register This register configures the SYSTICK peripheral clock. The SYSTICK timer clock can be shut down by setting the DIV bits to 0x0 ...
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... NXP Semiconductors Table 28. Bit Symbol 1:0 SEL 31:2 - 3.5.24 USB clock source update enable register This register updates the clock source of the USB with the new input clock after the USBCLKSEL register has been written to. In order for the update to take effect, first write a zero to the USBCLKUEN register and then write a one to USBCLKUEN ...
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... NXP Semiconductors Table 31. Bit Symbol 1:0 SEL 31:2 - 3.5.27 WDT clock source update enable register This register updates the clock source of the watchdog timer with the new input clock after the WDTCLKSEL register has been written to. In order for the update to take effect at the input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write a one to WDTCLKUEN ...
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... NXP Semiconductors Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 34. Bit Symbol 1:0 SEL 31:2 - 3.5.30 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTCLKSEL register has been written to ...
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... NXP Semiconductors 3.5.32 POR captured PIO status register 0 The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1, and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of one GPIO pin. This register is a read-only status register. ...
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... NXP Semiconductors Table 39. Bit Symbol 3:2 BODINTVAL 4 BODRSTENA 31:5 - 3.5.35 System tick counter calibration register Table 40. Bit Symbol 25:0 CAL 31:26 - 3.5.36 Start logic edge control register 0 The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11) and 1 (PIO1_0 to PIO1_11) and the lower 8 inputs of port 2 (PIO2_0 to PIO2_7). This ...
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... NXP Semiconductors Table 41. Bit Symbol 11:1 APRPIO0_11 to APRPIO0_1 12 APRPIO1_0 23:13 APRPIO1_11 to APRPIO1_1 24 APRPIO2_0 31:25 APRPIO2_7 to APRPIO2_1 3.5.37 Start logic signal enable register 0 This STARTERP0 register enables or disables the start signal bits in the start logic. The bit assignment is identical to Table 42. Bit Symbol ...
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... NXP Semiconductors Table 42. Bit Symbol 31:25 ERPIO2_7 to ERPIO2_1 3.5.38 Start logic reset register 0 Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit assignment is identical to clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt for waking up from Deep-sleep mode ...
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... NXP Semiconductors Table 44. Bit Symbol 0 SRPIO0_0 11:1 SRPIO0_11 to SRPIO0_1 12 SRPIO1_0 23:13 SRPIO1_11 to SRPIO1_1 24 SRPIO2_0 31:25 SRPIO2_7 to SRPIO2_1 3.5.40 Start logic edge control register 1 The STARTAPRP1 register controls the start logic inputs of ports 2 (PIO2_8 to PIO2_11) and 3 (PIO3_0 to PIO3_3). This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge, respectively, for the start-up logic ...
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... NXP Semiconductors Table 45. Bit Symbol 3:1 APRPIO2_11 to APRPIO2_9 4 APRPIO3_0 7:5 APRPIO3_3 to APRPIO3_1 31:8 - 3.5.41 Start logic signal enable register 1 This STARTERP1 register enables or disables the start signal bits in the start logic. The bit assignment is identical to Table 46. Bit Symbol 0 ERPIO2_8 3:1 ERPIO2_11 to ...
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... NXP Semiconductors Table 47. Bit Symbol 0 RSRPIO2_8 3:1 RSRPIO2_11 to RSPIO2_9 4 RSRPIO3_0 7:5 RSRPIO3_3 to RSRPIO3_1 31:8 - 3.5.43 Start logic status register 1 This register reflects the status of the enabled start signals. The bit assignment is identical to Table 45. Table 48. Bit Symbol 0 SRPIO2_8 3:1 SRPIO2_11 to SRPIO2_7 4 SRPIO3_0 ...
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... NXP Semiconductors 3.5.44 Deep-sleep mode configuration register This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode. This register must be initialized at least once before entering Deep-sleep mode with one of the four values shown in Table 49 ...
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... NXP Semiconductors Table 50. Bit Symbol 6 WDTOSC_PD 11:7 - 31:12 - 3.5.45 Wake-up configuration register The bits in this register can be programmed to determine the state the chip must enter when it is waking up from Deep-sleep mode. Remark: Reserved bits in this register must always be written as indicated. This register must be initialized correctly before entering Deep-sleep mode ...
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... NXP Semiconductors Table 51. Bit Symbol 7 SYSPLL_PD 8 USBPLL_PD USBPAD_PD 11 - 31:12 - 3.5.46 Power-down configuration register The bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC ...
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... NXP Semiconductors Table 52. Bit Symbol 4 ADC_PD 5 SYSOSC_PD 6 WDTOSC_PD 7 SYSPLL_PD 8 USBPLL_PD USBPAD_PD 11 - 31:12 - [1] The system oscillator must be powered up and selected for the USB PLL to create a stable USB clock (see Table 18). 3.5.47 Device ID register This device ID register is a read-only register and contains the device ID for each LPC13xx part ...
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... NXP Semiconductors 3.6 Reset Reset has four sources on the LPC13xx: the RESET pin, Watchdog Reset, Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once ...
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... NXP Semiconductors 3.8.1.1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices: • The SYSAHBCLKCTRL register controls which memories and peripherals are running • The power to various analog blocks (USB, PLL, oscillators, the ADC, the BOD circuit, ...
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... NXP Semiconductors 3.8.3 Deep-sleep mode In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG register. ...
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... NXP Semiconductors 3.8.3.3 Wake-up from Deep-sleep mode The microcontroller can wake up from Deep-sleep mode in the following ways: • Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 and PIO1_0 can be enabled as inputs to the start logic. The start logic does not require any clocks and generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode. • ...
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... NXP Semiconductors 3.8.4.3 Wake-up from Deep power-down mode Pulling the WAKEUP pin LOW wakes up the LPC13xx from Deep power-down, and the chip goes through the entire reset process 1. On the WAKEUP pin, transition from HIGH to LOW. – The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the chip re-boots ...
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... NXP Semiconductors output pin is also monitored by the start logic and can trigger a wake-up interrupt if that pin is enabled in the NVIC and the start logic trigger is configured accordingly in the start logic edge control register (see The following steps must be performed to configure the counter/timer and create a timed Deep-sleep self-wake-up event: 1 ...
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... NXP Semiconductors The block diagram of this PLL is shown MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the current controlled oscillator (CCO), which generates the main clock and optionally two additional phases ...
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... NXP Semiconductors spikes or drops in the frequency of the output clock. The recommended way of changing between divider settings is to power down the PLL, adjust the divider settings and then let the PLL start up again. 3.10.4 Frequency selection The PLL frequency equations use the following parameters (also see Table 54 ...
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... NXP Semiconductors Table 55. PLL input clock sys_pllclkin (Fclkin) 12 MHz 12 MHz 12 MHz 12 MHz 3.10.4.2 Power-down mode In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When ...
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UM10375 Chapter 4: LPC13xx Power Management Unit (PMU) Rev. 2 — 7 July 2010 4.1 Introduction The PMU controls the Deep power-down mode. Four general purpose register in the PMU can be used to retain data during Deep power-down mode. ...
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... NXP Semiconductors Table 58. Bit Symbol 11 DPDFLAG 31:12 - 4.2.2 General purpose registers The general purpose registers retain data through the Deep power-down mode when power is still applied to the V Only a “cold” boot when all power has been completely removed from the chip will reset the general purpose registers ...
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UM10375 Chapter 5: LPC13xx Interrupt controller Rev. 2 — 7 July 2010 5.1 How to read this chapter Interrupts 47 and 48 in interrupts are reserved on parts LPC1311/13. The implementation of start logic wake-up interrupts depends on how many ...
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... NXP Semiconductors Table 61. Exception Number [1] See Section 3.1 UM10375 User manual Connection of interrupt sources to the Vectored Interrupt Controller Vector Function Flag(s) Offset start logic wake-up Each interrupt is connected to a PIO input pin serving interrupts as wake-up pin from Deep-sleep mode (see Section 3.5.36 Interrupts are connected to PIO0_0 to PIO0_11 ...
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... NXP Semiconductors 5.5 Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3. The vector table may be located anywhere within the bottom Cortex-M3 address space ...
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... NXP Semiconductors 5.6 Register description The following table summarizes the registers in the NVIC as implemented in the LPC13xx. The Cortex-M3 User Guide provides a functional description of the NVIC. Table 62. Register overview: NVIC (base address 0xE000 E000) Name Access Address Description offset ISER0 RW 0x100 Interrupt Set-Enable Register 0. This register allows enabling interrupts and reading back the interrupt enables for specific peripheral functions ...
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... NXP Semiconductors Table 62. Register overview: NVIC (base address 0xE000 E000) Name Access Address Description offset IPR9 RW 0x424 Interrupt Priority Registers 9 This register allows assigning a priority to each interrupt. Each register contains the 5-bit priority fields for 4 interrupts. IPR10 RW 0x428 Interrupt Priority Registers 10 This register allows assigning a priority to each interrupt ...
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... NXP Semiconductors Table 63. Bit Name 15 ISE_PIO1_3 16 ISE_PIO1_4 17 ISE_PIO1_5 18 ISE_PIO1_6 19 ISE_PIO1_7 20 ISE_PIO1_8 21 ISE_PIO1_9 22 ISE_PIO1_10 23 ISE_PIO1_11 24 ISE_PIO2_0 25 ISE_PIO2_1 26 ISE_PIO2_2 27 ISE_PIO2_3 28 ISE_PIO2_4 29 ISE_PIO2_5 30 ISE_PIO2_6 31 ISE_PIO2_7 5.6.2 Interrupt Set-Enable Register 1 The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ...
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... NXP Semiconductors Table 64. Bit Name 11 ISE_CT32B0 12 ISE_CT32B1 13 ISE_SSP 14 ISE_UART 15 ISE_USBIRQ 16 ISE_USBFRQ 17 ISE_ADC 18 ISE_WDT 19 ISE_BOD ISE_PIO_3 22 ISE_PIO_2 23 ISE_PIO_1 24 ISE_PIO_0 31:25 - 5.6.3 Interrupt Clear-Enable Register 0 The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1 ...
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... NXP Semiconductors Table 65. Bit Name 12 ICE_PIO1_0 13 ICE_PIO1_1 14 ICE_PIO1_2 15 ICE_PIO1_3 16 ICE_PIO1_4 17 ICE_PIO1_5 18 ICE_PIO1_6 19 ICE_PIO1_7 20 ICE_PIO1_8 21 ICE_PIO1_9 22 ICE_PIO1_10 23 ICE_PIO1_11 24 ICE_PIO2_0 25 ICE_PIO2_1 26 ICE_PIO2_2 27 ICE_PIO2_3 28 ICE_PIO2_4 29 ICE_PIO2_5 30 ICE_PIO2_6 31 ICE_PIO2_7 5.6.4 Interrupt Clear-Enable Register 1 register The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts ...
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... NXP Semiconductors Table 66. Bit Name 9 ICE_CT16B0 10 ICE_CT16B1 11 ICE_CT32B0 12 ICE_CT32B1 13 ICE_SSP 14 ICE_UART 15 ICE_USBIRQ 16 ICE_USBFRQ 17 ICE_ADC 18 ICE_WDT 19 ICE_BOD ICE_PIO_3 22 ICE_PIO_2 23 ICE_PIO_1 24 ICE_PIO_0 31:25 - 5.6.5 Interrupt Set-Pending Register 0 register The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their ...
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... NXP Semiconductors Table 67. Bit Name 7 ISP_PIO0_7 8 ISP_PIO0_8 9 ISP_PIO0_9 10 ISP_PIO0_10 11 ISP_PIO0_11 12 ISP_PIO1_0 13 ISP_PIO1_1 14 ISP_PIO1_2 15 ISP_PIO1_3 16 ISP_PIO1_4 17 ISP_PIO1_5 18 ISP_PIO1_6 19 ISP_PIO1_7 20 ISP_PIO1_8 21 ISP_PIO1_9 22 ISP_PIO1_10 23 ISP_PIO1_11 24 ISP_PIO2_0 25 ISP_PIO2_1 26 ISP_PIO2_2 27 ISP_PIO2_3 28 ISP_PIO2_4 29 ISP_PIO2_5 30 ISP_PIO2_6 31 ISP_PIO2_7 5.6.6 Interrupt Set-Pending Register 1 register The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts ...
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... NXP Semiconductors Table 68. Bit Name 0 ISP_PIO2_8 1 ISP_PIO2_9 2 ISP_PIO2_10 3 ISP_PIO2_11 4 ISP_PIO3_0 5 ISP_PIO3_1 6 ISP_PIO3_2 7 ISP_PIO3_3 8 ISP_I2C0 9 ISP_CT16B0 10 ISP_CT16B1 11 ISP_CT32B0 12 ISP_CT32B1 13 ISP_SSP 14 ISP_UART 15 ISP_USBIRQ 16 ISP_USBFRQ 17 ISP_ADC 18 ISP_WDT 19 ISP_BOD ISP_PIO_3 22 ISP_PIO_2 23 ISP_PIO_1 24 ISP_PIO_0 31:25 - 5.6.7 Interrupt Clear-Pending Register 0 register The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts ...
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... NXP Semiconductors Table 69. Bit Name 0 ICP_PIO0_0 1 ICP_PIO0_1 2 ICP_PIO0_2 3 ICP_PIO0_3 4 ICP_PIO0_4 5 ICP_PIO0_5 6 ICP_PIO0_6 7 ICP_PIO0_7 8 ICP_PIO0_8 9 ICP_PIO0_9 10 ICP_PIO0_10 11 ICP_PIO0_11 12 ICP_PIO1_0 13 ICP_PIO1_1 14 ICP_PIO1_2 15 ICP_PIO1_3 16 ICP_PIO1_4 17 ICP_PIO1_5 18 ICP_PIO1_6 19 ICP_PIO1_7 20 ICP_PIO1_8 21 ICP_PIO1_9 22 ICP_PIO1_10 23 ICP_PIO1_11 24 ICP_PIO2_0 25 ICP_PIO2_1 26 ICP_PIO2_2 27 ICP_PIO2_3 28 ICP_PIO2_4 29 ICP_PIO2_5 30 ICP_PIO2_6 31 ICP_PIO2_7 UM10375 User manual Interrupt Clear-Pending Register 0 register (ICPR0 - address 0xE000 E280) bit ...
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... NXP Semiconductors 5.6.8 Interrupt Clear-Pending Register 1 register The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers Section 5.6.6). ...
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... NXP Semiconductors 5.6.9 Interrupt Active Bit Register 0 The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. The remaining ...
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... NXP Semiconductors 5.6.10 Interrupt Active Bit Register 1 The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. ...
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... NXP Semiconductors 5.6.11 Interrupt Priority Register 0 The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 73. Bit Name 2:0 Unimplemented 7:3 IP_PIO0_0 10:8 Unimplemented 15:11 IP_PIO0_1 18:16 Unimplemented 23:19 IP_PIO0_2 ...
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... NXP Semiconductors 5.6.13 Interrupt Priority Register 2 The IPR2 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 75. Bit Name 2:0 Unimplemented 7:3 IP_PIO0_8 10:8 Unimplemented 15:11 IP_PIO0_9 18:16 Unimplemented 23:19 IP_PIO0_10 ...
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... NXP Semiconductors 5.6.15 Interrupt Priority Register 4 The IPR4 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 77. Bit Name 2:0 Unimplemented 7:3 IP_PIO1_4 10:8 Unimplemented 15:11 IP_PIO1_5 18:16 Unimplemented 23:19 IP_PIO1_6 ...
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... NXP Semiconductors 5.6.17 Interrupt Priority Register 6 The IPR6 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 79. Bit Name 2:0 Unimplemented 7:3 IP_PIO2_0 10:8 Unimplemented 15:11 IP_PIO2_1 18:16 Unimplemented 23:19 IP_PIO2_2 ...
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... NXP Semiconductors 5.6.19 Interrupt Priority Register 8 The IPR8 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 81. Bit Name 2:0 Unimplemented 7:3 IP_PIO2_8 10:8 Unimplemented 15:11 IP_PIO2_9 18:16 Unimplemented 23:19 IP_PIO2_10 ...
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... NXP Semiconductors 5.6.21 Interrupt Priority Register 10 The IPR10 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 83. Bit Name 2:0 Unimplemented 7:3 IP_I2C 10:8 Unimplemented 15:11 IP_CT16B0 18:16 Unimplemented 23:19 IP_CT16B1 ...
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... NXP Semiconductors 5.6.23 Interrupt Priority Register 12 The IPR12 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 85. Bit Name 2:0 Unimplemented 7:3 IP_USNFIQ 10:8 Unimplemented 15:11 IP_ADC 18:16 Unimplemented 23:19 IP_WDT ...
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... NXP Semiconductors 5.6.25 Interrupt Priority Register 14 The IPR14 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 87. Bit Name 2:0 Unimplemented 7:3 IP_PIO0 31:10 - 5.6.26 Software Trigger Interrupt Register The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers ...
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UM10375 Chapter 6: LPC13xx I/O configuration Rev. 2 — 7 July 2010 6.1 How to read this chapter The implementation of the I/O configuration registers varies for different LPC13xx parts and packages. See not used in all parts or packages. ...
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... NXP Semiconductors pin configured as digital output driver pin configured as digital input pin configured as analog input Fig 5. Standard I/O pin configuration 6.3.1 Pin function The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000 peripheral function. If the pins are GPIO pins, the GPIOnDIR registers determine whether the pin is configured as an input or output (see pin direction is controlled automatically depending on the pin’ ...
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... NXP Semiconductors 6.3.3 Hysteresis The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers (see the LPC1311/13/43/44 data sheet for details). If the external pad supply voltage V can be enabled or disabled use the pin in input mode. ...
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... NXP Semiconductors Table 90. Register overview: I/O configuration block (base address 0x4004 4000) Name Access IOCON_PIO0_1 R/W IOCON_PIO1_8 R/W - R/W IOCON_PIO0_2 R/W IOCON_PIO2_7 R/W IOCON_PIO2_8 R/W IOCON_PIO2_1 R/W IOCON_PIO0_3 R/W IOCON_PIO0_4 R/W IOCON_PIO0_5 R/W IOCON_PIO1_9 R/W IOCON_PIO3_4 R/W IOCON_PIO2_4 R/W IOCON_PIO2_5 R/W ...
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... NXP Semiconductors Table 90. Register overview: I/O configuration block (base address 0x4004 4000) Name Access IOCON_PIO1_11 R/W IOCON_PIO3_2 R/W IOCON_PIO1_5 R/W IOCON_PIO1_6 R/W IOCON_PIO1_7 R/W IOCON_PIO3_3 R/W IOCON_SCKLOC R/W Table 91. Port pin PIO0_0 PIO0_1 PIO0_2 PIO0_3 PIO0_4 PIO0_5 PIO0_6 PIO0_7 PIO0_8 PIO0_9 ...
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... NXP Semiconductors Table 91. Port pin PIO2_6 PIO2_7 PIO2_8 PIO2_9 PIO2_10 PIO2_11 PIO3_0 PIO3_1 PIO3_2 PIO3_3 PIO3_4 PIO3_5 [1] On LPC134x, PIO3_4 and PIO3_5 are not available. The corresponding pins are used for the USB D+ and D− functions. 6.4.1 I/O configuration registers IOCON_PIOn For details on the I/O configuration settings, see Table 92 ...
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... NXP Semiconductors Table 93. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 94. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual IOCON_PIO2_0 register (IOCON_PIO2_0, address 0x4004 4008) bit description Value Description Selects pin function. 000 Selects function PIO2_0 001 ...
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... NXP Semiconductors Table 95. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 96. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual IOCON_PIO0_1 register (IOCON_PIO0_1, address 0x4004 4010) bit description Value Description Selects pin function 000 Selects function PIO0_1 001 ...
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... NXP Semiconductors Table 97. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 98. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual IOCON_PIO0_2 register (IOCON_PIO0_2, address 0x4004 401C) bit description Value Description Selects pin function 000 Selects function PIO0_2 001 ...
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... NXP Semiconductors Table 99. Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description Value Description Selects pin function 000 Selects function PIO2_8 001 to Reserved 111 Selects function mode (on-chip pull-up/pull-down resistor control) ...
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... NXP Semiconductors Table 100. IOCON_PIO2_1 register (IOCON_PIO2_1, address 0x4004 4028) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 101. IOCON_PIO0_3 register (IOCON_PIO0_3, address 0x4004 402C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 102. IOCON_PIO0_4 register (IOCON_PIO0_4, address 0x4004 4030) bit description Bit Symbol 2:0 FUNC 7:3 - 9:8 I2CMODE 31:10 - [1] Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). Table 103. IOCON_PIO0_5 register (IOCON_PIO0_5, address 0x4004 4034) bit description ...
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... NXP Semiconductors Table 104. IOCON_PIO1_9 register (IOCON_PIO1_9 address 0x4004 4038) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 105. IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 106. IOCON_PIO2_4 register (IOCON_PIO2_4, address 0x4004 4040) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 107. IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 108. IOCON_PIO3_5 register (IOCON_PIO3_5, address 0x4004 4048) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 109. IOCON_PIO0_6 register (IOCON_PIO0_6, address 0x4004 404C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 110. IOCON_PIO0_7 register (IOCON_PIO0_7, address 0x4004 4050) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 111. IOCON_PIO2_9 register (IOCON_PIO2_9, address 0x4004 4054) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 112. IOCON_PIO2_10 register (IOCON_PIO2_10, address 0x4004 4058) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 113. IOCON_PIO2_2 register (IOCON_PIO2_2, address 0x4004 405C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 114. IOCON_PIO0_8 register (IOCON_PIO0_8, address 0x4004 4060) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 115. IOCON_PIO0_9 register (IOCON_PIO0_9, address 0x4004 4064) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 116. IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004 Bit Symbol Value 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual 4068) bit description Description Selects pin function 000 Selects function SWCLK 001 Selects function PIO0_10 010 Selects function SCK (only if pin ...
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... NXP Semiconductors Table 117. IOCON_PIO1_10 register (IOCON_PIO1_10, address 0x4004 406C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - Table 118. IOCON_PIO2_11 register (IOCON_PIO2_11, address 0x4004 4070) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 119. IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - UM10375 User manual description Value Description Selects pin function 000 Selects function R. This function is reserved. Select one of the alternate functions below. ...
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... NXP Semiconductors Table 120. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0, address 0x4004 4078) bit Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - UM10375 User manual description Value Description Selects pin function 000 Selects function R. This function is reserved. Select one of the alternate functions below. ...
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... NXP Semiconductors Table 121. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1, address 0x4004 407C) bit Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - UM10375 User manual description Value Description Selects pin function 000 Selects function R. This function is reserved. Select one of the alternate functions below. ...
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... NXP Semiconductors Table 122. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2, address 0x4004 4080) bit Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - Table 123. IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 124. IOCON_PIO3_1 register (IOCON_PIO3_1, address 0x4004 4088) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 125. IOCON_PIO2_3 register (IOCON_PIO2_3, address 0x4004 408C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 126. IOCON_SWDIO_PIO1_3 register (IOCON_SWDIO_PIO1_3, address 0x4004 4090) Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - UM10375 User manual bit description Value Description Selects pin function 000 Selects function SWDIO 001 Selects function PIO1_3 010 Selects function AD4 ...
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... NXP Semiconductors Table 127. IOCON_PIO1_4 register (IOCON_PIO1_4, address 0x4004 4094) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - [1] This pin functions as WAKEUP pin if the LPC13xx is in Deep power-down mode regardless of the value of FUNC. UM10375 User manual Value Description ...
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... NXP Semiconductors Table 128. IOCON_PIO1_11 register (IOCON_PIO1_11, address 0x4004 4098) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS ADMODE 31:8 - Table 129. IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 130. IOCON_PIO1_5 register (IOCON_PIO1_5, address 0x4004 40A0) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 131. IOCON_PIO1_6 register (IOCON_PIO1_6, address 0x4004 40A4) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - UM10375 User manual ...
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... NXP Semiconductors Table 132. IOCON_PIO1_7 register (IOCON_PIO1_7, address 0x4004 40A8) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - Table 133. IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description Bit Symbol 2:0 FUNC 4:3 MODE 5 HYS 6 - 31:7 - 6.4.1.1 IOCON SCK location register This register is used to select a pin among three possible choices for the SSP SCK function ...
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... NXP Semiconductors Remark: Note that once the pin location has been selected, the function still must be set to SCK in the corresponding IOCONF registers for the SCK to be usable on that pin. Table 134. IOCON SCK location register (IOCON_SCKLOC, address 0x4004 40B0) bit Bit ...
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UM10375 Chapter 7: LPC13xx Pin configuration Rev. 2 — 7 July 2010 7.1 How to read this chapter The LPC13xx parts are available in LQFP48 and HVQFN33 packages. The LPC1342/43 parts have dedicated USB pins and additional USB functions on ...
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... NXP Semiconductors 7.2 LPC134x pin configuration PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE XTALIN XTALOUT PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 Fig 6. LPC1343 LQFP48 package UM10375 User manual 1 PIO2_6 LPC1343FBD48 PIO2_7 PIO2_8 12 All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 July 2010 UM10375 Chapter 7: LPC13xx Pin configuration ...
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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 Fig 7. LPC1342/43 HVQFN33 package UM10375 User manual terminal 1 index area PIO2_0/DTR 1 RESET/PIO0_0 XTALIN LPC1342FHN33 5 XTALOUT LPC1343FHN33 Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 July 2010 UM10375 Chapter 7: LPC13xx Pin configuration ...
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... NXP Semiconductors 7.3 LPC131x pin configuration PIO2_6 PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V SS XTALIN XTALOUT V DD PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 8. LPC1313 LQFP48 package UM10375 User manual LPC1313FBD48 All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 July 2010 UM10375 Chapter 7: LPC13xx Pin configuration ...
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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2 PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 Fig 9. LPC1311/13 HVQFN33 package 7.4 Pin description In Table 136 and special function pins appear at the end. The default function of each pin is always the first function listed in the description column or the first function of each pin symbol. Each pin function can be set through the ...
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... NXP Semiconductors 7.4.1 LQFP48 packages Table 136. LPC1313/43 LQFP48 pin description table Symbol Pin [1] RESET/PIO0_0 3 [2] PIO0_1/CLKOUT/ 4 CT32B0_MAT2/ USB_FTOGGLE [2] PIO0_2/SSEL/ 10 CT16B0_CAP0 [2] PIO0_3/USB_VBUS 14 [3] PIO0_4/SCL 15 [3] PIO0_5/SDA 16 [2] PIO0_6/USB_CONNECT/ 22 SCK [2] PIO0_7/CTS 23 [2] PIO0_8/MISO/ 27 CT16B0_MAT0 [2] PIO0_9/MOSI/ 28 CT16B0_MAT1/ SWO [2] SWCLK/PIO0_10/ 29 SCK/CT16B0_MAT2 UM10375 User manual ...
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... NXP Semiconductors Table 136. LPC1313/43 LQFP48 pin description table Symbol Pin [4] R/PIO0_11/ 32 AD0/CT32B0_MAT3 [4] R/PIO1_0/ 33 AD1/CT32B1_CAP0 [4] R/PIO1_1/ 34 AD2/CT32B1_MAT0 [4] R/PIO1_2/ 35 AD3/CT32B1_MAT1 [4] SWDIO/PIO1_3/AD4/ 39 CT32B1_MAT2 [4] PIO1_4/AD5/ 40 CT32B1_MAT3/WAKEUP [2] PIO1_5/RTS/ 45 CT32B0_CAP0 [2] PIO1_6/RXD/ 46 CT32B0_MAT0 [2] PIO1_7/TXD/ 47 CT32B0_MAT1 [2] PIO1_8/CT16B1_CAP0 9 [2] PIO1_9/CT16B1_MAT0 17 UM10375 User manual …continued Type Description - R — Reserved. Configure for an alternate function in the IOCONFIG block. ...
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... NXP Semiconductors Table 136. LPC1313/43 LQFP48 pin description table Symbol Pin [4] PIO1_10/AD6/ 30 CT16B1_MAT1 [4] PIO1_11/AD7 42 [2] PIO2_0/DTR 2 [2] PIO2_1/DSR 13 [2] PIO2_2/DCD 26 [2] PIO2_3/RI 38 [2] PIO2_4 18 [2] PIO2_4 19 [2] PIO2_5 21 [2] PIO2_5 20 [2] PIO2_6 1 [2] PIO2_7 11 [2] PIO2_8 12 [2] PIO2_9 24 [2] PIO2_10 25 [2] ...
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... NXP Semiconductors 2 2 [3] I C-bus pads compliant with the I C-bus specification for I [ tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. ...
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... NXP Semiconductors Table 137. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin [2] PIO0_9/MOSI/ 18 CT16B0_MAT1/ SWO [2] SWCLK/PIO0_10/SCK/ 19 CT16B0_MAT2 [4] R/PIO0_11/AD0/ 21 CT32B0_MAT3 [4] R/PIO1_0/AD1/ 22 CT32B1_CAP0 [4] R/PIO1_1/AD2/ 23 CT32B1_MAT0 [4] R/PIO1_2/AD3/ 24 CT32B1_MAT1 [4] SWDIO/PIO1_3/AD4/ 25 CT32B1_MAT2 [4] PIO1_4/AD5/ 26 CT32B1_MAT3/WAKEUP [2] PIO1_5/RTS/ 30 CT32B0_CAP0 [2] PIO1_6/RXD/ 31 CT32B0_MAT0 UM10375 User manual …continued Type Description I/O PIO0_9 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 137. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin [2] PIO1_7/TXD/ 32 CT32B0_MAT1 [2] PIO1_8/CT16B1_CAP0 7 [2] PIO1_9/CT16B1_MAT0 12 [4] PIO1_10/AD6/ 20 CT16B1_MAT1 [4] PIO1_11/AD7 27 [2] PIO2_0/DTR 1 [2] PIO3_2 28 [2] PIO3_4 13 [2] PIO3_5 14 [5] USB_DM 13 [5] USB_DP [6] XTALIN 4 [6] XTALOUT [1] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
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UM10375 Chapter 8: LPC13xx General Purpose I/O (GPIO) Rev. 2 — 7 July 2010 8.1 How to read this chapter The number of GPIO pins available on each port depends on the LPC13xx part and the package. See Table 138. ...
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... NXP Semiconductors Table 140. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000; port 3: 0x5003 0000) Name Access GPIOnDATA R/W GPIOnDATA R GPIOnDIR R/W GPIOnIS R/W GPIOnIBE R/W GPIOnIEV R/W GPIOnIE R/W GPIOnRIS R GPIOnMIS R GPIOnIC 8.4.1 GPIO data register The GPIOnDATA register holds the current state of the pin (HIGH or LOW), independently of whether the pin is configured as an GPIO input or output or as another digital function ...
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... NXP Semiconductors • pin is configured as another digital function (input or output), a write to the GPIOnDATA register has no effect on the pin level. A read returns the current state of the pin even configured as an output. This means that by reading the GPIOnDATA register, the digital output or input value of a function other than GPIO on that pin can be observed ...
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... NXP Semiconductors 8.4.4 GPIO interrupt both edges sense register Table 144. GPIOnIBE register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003 Bit Symbol Value 11:0 IBE 31:12 - 8.4.5 GPIO interrupt event register Table 145. GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003 ...
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... NXP Semiconductors Table 147. GPIOnIRS register (GPIO0IRS, address 0x5000 8014 to GPIO3IRS, address 0x5003 Bit Symbol Value 11:0 RAWST 31:12 - 8.4.8 GPIO masked interrupt status register Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input pins has been generated or that the interrupt is masked ...
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... NXP Semiconductors 8.5 Functional description 8.5.1 Write/read data operations In order for software to be able to set GPIO bits without affecting any other pins in a single write operation, bits [13: 14-bit wide address bus are used to create a 12-bit wide mask for write and read operations on the 12 GPIO pins for each port. Only GPIOnDATA bits masked by 1 are affected by read and write operations ...
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... NXP Semiconductors Read operation If the address bit associated with the GPIO data bit is HIGH, the value is read. If the address bit is LOW, the GPIO data bit is read as 0: Reading a port DATA register yields the state of port pins 11:0 ANDed with address bits 13:2. ...
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UM10375 Chapter 9: LPC13xx USB device controller Rev. 2 — 7 July 2010 9.1 How to read this chapter The USB device controller is available on parts LPC1342 and LPC1343 only. 9.2 Basic configuration The USB device is configured using ...
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... NXP Semiconductors Table 150. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description EP_RAM FS LED LS MPS NAK PLL RAM SOF SIE SRAM UDCA USB 9.4 Features • Fully compliant with the USB 2.0 specification (full-speed). • Supports 10 physical (5 logical) endpoints. ...
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... NXP Semiconductors 9.6 General description The architecture of the USB device controller is shown below in BUS MASTER INTERFACE REGISTER INTERFACE register interface (APB slave) USB DEVICE BLOCK Fig 12. USB device controller block diagram 9.6.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional USB_DP and USB_DM signals of the USB bus ...
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... NXP Semiconductors 9.6.5 Register interface The Register Interface allows the CPU to control the operation of the USB Device Controller. It also provides a way to write transmit data to the controller and read receive data from the controller. 9.6.6 SoftConnect The connection to the USB is accomplished by bringing USB_DP (for a full-speed device) HIGH through a 1 ...
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... NXP Semiconductors For an OUT transaction, the USB ATX receives the bi-directional USB_DP and USB_DM signals of the USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and converts it into a parallel data stream. The parallel data is written to the corresponding endpoint buffer ...
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... NXP Semiconductors Table 153. USB device controller clock sources Source ahb_sys_clk usb_clk (see Table 10) The usb_clk clock can be either provided by the main clock or a dedicated USB PLL (see Figure 3). The USB PLL can be powered down not used for the usb_clk in the PDRUNCFG register 9 ...
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... NXP Semiconductors . USB block USB_NeedClk USB_MainClk PCLK SYSAHBCLKCTRL[14] 48 Mhz USB_NeedClk Fig 14. USB clocking 9.9.4 Remote wake-up The USB block supports software initiated remote wake-up. Remote wake-up involves a resume signal initiated from the device. This is done by resetting the suspend bit in the Device Status register. Before writing into the register, ...
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... NXP Semiconductors Table 154. Register overview: USB device (base address 0x4002 0000) Name Device interrupt registers USBDevIntSt USBDevIntEn USBDevIntClr USBDevIntSet SIE command registers USBCmdCode USBCmdData USB data transfer registers USBRxData USBTxData USBRxPLen USBTxPLen USBCtrl Miscellaneous registers USBDevFIQSel [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. ...
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... NXP Semiconductors Table 156. USB Device Interrupt Status register (USBDevIntSt - address 0x4002 0000) bit Bit Symbol 0 FRAME 1 EP0 2 EP1 3 EP2 4 EP3 5 EP4 6 EP5 7 EP6 8 EP7 9 DEV_STAT 10 CC_EMPTY The command code register (USBCmdCode) is empty (New 11 CD_FULL 12 RxENDPKT The current packet in the endpoint buffer is transferred to the ...
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... NXP Semiconductors Table 158. USB Device Interrupt Clear register (USBDevIntClr - address 0x4002 0008) bit Bit Symbol 31:0 See 9.10.1.4 USB Device Interrupt Set register (USBDevIntSet - 0x4002 000C) Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing a zero has no effect USBDevIntSet is a write only register ...
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... NXP Semiconductors Table 160. USB Command Code register (USBCmdCode - address 0x4002 0010) bit Bit Symbol 23:16 CMD_CODE/ CMD_WDATA 31:24 - 9.10.2.2 USB Command Data register (USBCmdData - 0x4002 0014) This register contains the data retrieved after executing a SIE command. When the data is ready to be read, the CD_FULL bit of the USBDevIntSt register is set. See details ...
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... NXP Semiconductors writing this register, the data is written to the selected endpoint buffer. The data is in little endian format: the first byte sent on the USB bus will be the least significant byte of USBTxData. USBTxData is a write only register. Table 163. USB Transmit Data register (USBTxData - address 0x4002 001C) bit description ...
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... NXP Semiconductors Table 165. USB Transmit Packet Length register (USBTxPLen - address 0x4002 0024) bit Bit Symbol 9:0 PKT_LNGTH - 31:10 - 9.10.3.5 USB Control register (USBCtrl - 0x4002 0028) This register controls the data transfer operation of the USB device. It selects the endpoint buffer that is accessed by the USBRxData and USBTxData registers and enables reading and writing them ...
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... NXP Semiconductors If the software makes the Read Enable bit low midway, the reading will be terminated. In this case the data will remain in the RAM. When the Read Enable signal is made high again for this endpoint, data will be read from the beginning. For writing data to an endpoint buffer, the Write Enable bit should be made high and software should write to the Tx Packet Length register the number of bytes it is going to send in the packet ...
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... NXP Semiconductors Table 167. USB Device FIQ Select register (USBDevFIQSel - address 0x4002 002C) bit Bit Symbol 1 BULKOUT 2 BULKIN 31:3 - [1] Remark: For logical endpoint 3 (physical endpoints 6 and 7) only. 9.11 Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action) ...
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... NXP Semiconductors USBCmdCode = 0x00F50200; while (!(USBDevIntSt & 0x20)); // Wait for CDFULL. Temp = USBCmdData; USBDevIntClr = 0x20; CurFrameNum = CurFrameNum | (Temp << 8); Here is an example of the Set Address command (writing 1 byte): USBDevIntClr = 0x10; USBCmdCode = 0x00D00500; while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY. USBDevIntClr = 0x10; ...
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... NXP Semiconductors 9.11.1 Set Address (Command: 0xD0, Data: write 1 byte) The Set Address command is used to set the USB assigned address and enable the (embedded) function. The address set in the device will take effect after the status stage of the control transaction. After a bus reset, DEV_ADDR is set to 0x00, and DEV_EN is set to 1 ...
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... NXP Semiconductors Table 171. Set Mode command description Bit Symbol 2 INAK_CO 3 INAK_AI 4 INAK_AO 7:5 - 9.11.4 Read Interrupt Status (Command: 0xF4, Data: read 2 bytes) Table 172. Read interrupt Status byte 1 command description Bit Symbol 0 EP0 1 EP1 2 EP2 3 EP3 4 EP4 7:5 - Table 173. Read interrupt Status byte 2 command description ...
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... NXP Semiconductors • In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. 9.11.6 Read Chip ID (Command: 0xFD, Data: read 2 bytes) The Chip ID is 16-bit wide. It returns the value the chip ID (LSB first). ...
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... NXP Semiconductors Table 174. Set Device Status command description Bit Symbol 4 RST 7:5 - 9.11.8 Get Device Status (Command: 0xFE, Data: read 1 byte) The Get Device Status command returns the Device Status Register. Reading the device status returns 1 byte of data. The bit field definition is same as the Set Device Status ...
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... NXP Semiconductors Table 175. Get Error Code command description Bit Symbol Value 3 7:5 - 9.11.10 Select Endpoint (Command: 0x00 - 0x09 Data: read 1 byte (optional)) The Select Endpoint command initializes an internal pointer to the start of the selected buffer in EP_RAM. Optionally, this command can be followed by a data read, which returns some additional information on the packet(s) in the endpoint buffer(s) ...
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... NXP Semiconductors Table 176. Select Endpoint command description Bit Symbol 2 STP EPN 5 B_1_FULL 6 B_2_FULL 7 - 9.11.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x47, Data: read 1 byte) Commands 0x40 to 0x47 are identical to their Select Endpoint equivalents, with the following differences: • They clear the bit corresponding to the endpoint in the USBEpIntSt register. ...
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... NXP Semiconductors Table 177. Set Endpoint Status command description Bit Symbol RF_MO 7 CND_ST 9.11.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional)) When an OUT packet sent by the host has been received successfully, an internal hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by returning a NAK ...
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... NXP Semiconductors Table 178. Clear Buffer command description Bit Symbol Value Description 0 PO 7:1 - 9.11.14 Validate Buffer (Command: 0xFA, Data: none) When the CPU has written data into an IN buffer, software should issue a Validate Buffer command. This tells hardware that the buffer is ready for sending on the USB bus. ...
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... NXP Semiconductors 7. Enable the main system PLL by clearing bit 7 in PDAWAKECFG (see wait until the PLL clock is locked the USB PLL is used as the USB clock, do the following extra step: Configure USB PLL identically to the System PLL and select system clock source by setting 0x01 (use system oscillator) in USBPLLCLKSEL (see 9 ...
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... NXP Semiconductors Isochronous endpoint will have one packet of data to be transferred in every frame. This requires the data transfer has to be synchronized to the USB frame rather than packet arrival. The 1 KHz free running clock re synchronized on the incoming SoF tokens will generate an interrupt every millisecond. ...
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... NXP Semiconductors It is assumed that the Isochronous pipe is open at the reception of a request "Set Interface (alternate setting > 0)". This request is sent to the interface to which the isochronous endpoint belongs. This means that the device is expecting the first isochronous transfer within the millisecond ...
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... NXP Semiconductors 3. Software is still reading from B_1 when the host attempts to send a third packet. Since both B_1 and B_2 are full, the device hardware responds with a NAK. 4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer command to free B_1 to receive another packet. B_2 becomes the active buffer. ...
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... NXP Semiconductors 9. The device successfully sends the third packet from B_1 and generates an endpoint interrupt. 10. Software has no more packets to send simply clears the interrupt. 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. ...
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UM10375 Chapter 10: LPC13xx USB on-chip drivers Rev. 2 — 7 July 2010 10.1 How to read this chapter The USB device controller is available on parts LPC1342 and LPC1343 only. 10.2 Introduction The boot ROM contains a USB driver ...
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... NXP Semiconductors 10.3.2 USB initialization This function must be called by the application software after the clock and pin initialization. A pointer to the structure describing the USB device type is passed as a parameter to this function. The USB device type can be HID or MSC. The pointer is stored for future reference ...
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... NXP Semiconductors 0x1FFF 1FF8 Ptr to ROM Driver table ROM Driver Table Ptr to USB Driver Table 1 Ptr to Device Table 2 Ptr to Device Table 3 Ptr to Device Table n Fig 15. USB device driver pointer structure 10.4.1 USB mass storage driver The following steps illustrate the USB mass storage driver usage. A complete example is available in the LPC13xx code bundle ...
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... NXP Semiconductors MscDevInfo.MSC_Write = MSC_MemoryWrite; 5. Initialize the USB: DeviceInfo.DevType = USB_DEVICE_CLASS_STORAGE; DeviceInfo.DevDetailPtr = (uint32_t)&MscDevInfo; (*rom)->pUSBD->init(&DeviceInfo); 6. Initialize the mass storage state machine: (uint32_t *) BulkStage = 0x10000054; *BulkStage = 0x0; 7. Add the USB interrupt handler to your project: USB_IRQHandler(void) { (*rom)->pUSBD->isr(); } 8. Call USB connect: (*rom)-> ...
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... NXP Semiconductors DeviceInfo.DevDetailPtr = (uint32_t)&HidDevInfo; (*rom)->pUSBD->init(&DeviceInfo); 6. Add the USB interrupt handler to your project: USB_IRQHandler(void) { (*rom)->pUSBD->isr(); } 7. Call USB connect: USB Connect (*rom)->pUSBD->connect(TRUE); 10.5 USB driver structure definitions 10.5.1 ROM driver table The following structure is used to access the USB driver table stored in ROM: typedef struct _ROM { const USBD * pUSBD ...
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... NXP Semiconductors Table 179. USB device information class structure Member DevType DevDetailPtr 10.5.4 Mass storage device information The following structure is used to pass the MSC device information: typedef struct _MSC_DEVICE_INFO { uint16_t uint16_t uint16_t uint32_t StrDescPtr; uint32_t MSCInquiryStr; uint32_t BlockCount; uint32_t BlockSize; uint32_t MemorySize; ...
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... NXP Semiconductors Table 180. Mass storage device information class structure Member MemorySize MSC_Write MSC_Read 10.5.5 Human interface device information The following structure is used to pass the HID device information: typedef struct _HID_DEVICE_INFO { uint16_t uint16_t uint16_t uint32_t StrDescPtr; uint8_t uint8_t uint8_t void (*InReport)( uint8_t src[], uint32_t length); ...
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... NXP Semiconductors Table 181. Human interface device information class structure Member SampleInterval InReport OutReport 10.6 USB descriptors The USB driver reports several predefined descriptors during enumeration of the HID or MSC device types. Certain fields of the descriptor are user-defined. 10.6.1 Standard descriptor The USB driver reports the following predefined descriptor during enumeration of the HID or MSC device ...
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... NXP Semiconductors 10.6.2 Mass storage configuration, interface, and endpoint descriptors The USB driver reports the following descriptors during the enumeration process for a MSC device: Table 183. Mass storage descriptors Field Mass storage configuration descriptor bLength bDescriptorType wTotalLength bNumInterfaces bConfigurationValue 0x01 iConfiguration ...
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... NXP Semiconductors Table 184. HID descriptors Field HID configuration descriptor bLength bDescriptorType wTotalLength bNumInterfaces bConfigurationValue 0x01 iConfiguration bmAttributes bMaxPower HID interface descriptor bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface HID class descriptor bLength bDescriptorType bcdHID bCountryCode bNumDescriptors bDescriptorType wDescriptorLength ...
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... NXP Semiconductors Table 184. HID descriptors Field bInterval HID report descriptor Usage Page Usage Collection Logical Minimum Logical Maximum Report Size Report Count Usage Input Report Count Usage Output End Collection 10.6.4 Example descriptors Example HID descriptor USB_HID_StringDescriptor 0x04, USB_STRING_DESCRIPTOR_TYPE, 0x0409 ...
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... NXP Semiconductors Example MSC descriptor USB_ISP_StringDescriptor[] = {0x04,USB_STRING_DESCRIPTOR_TYPE,0x0409, /* Index 0x04: Manufacturer */ 0x1C,USB_STRING_DESCRIPTOR_TYPE, 'N',0,'X',0,'P',0,' ',0,'S',0,'e',0,'m',0,'i',0,'c',0,'o',0,'n',0,'d',0,' ',0, /* Index 0x20: Product */ 0x28, USB_STRING_DESCRIPTOR_TYPE, 'N',0,'X',0,'P',0,' ',0,'L',0,'P',0,'C',0,'1',0,'3',0,'X',0,'X',0, ' ',0,'I',0, 'F',0, 'L',0, 'A',0, 'S',0,'H',0,' ',0, ...
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UM10375 Chapter 11: LPC13xx UART Rev. 2 — 7 July 2010 11.1 How to read this chapter The UART block is identical for all LPC13xx parts. The DSR, DCD, and RI modem signals are pinned out for the LQFP48 packages ...
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... NXP Semiconductors 11.5 Clocking and power control The clocks and power to the UART block are controlled by two registers: 1. The UART block can be enabled or disabled through the System AHB clock control register bit 12 (see 2. The UART peripheral clock UART_PCLK is enabled in the UART clock divider ...
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... NXP Semiconductors Table 186. Register overview: UART (base address: 0x4000 8000) Name Access Address offset U0RBR RO 0x000 U0THR WO 0x000 U0DLL R/W 0x000 U0DLM R/W 0x004 U0IER R/W 0x004 U0IIR RO 0x008 U0FCR WO 0x008 U0LCR R/W 0x00C U0MCR R/W 0x010 U0LSR RO 0x014 U0MSR ...
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... NXP Semiconductors 11.6.1 UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0, Read Only) The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “ ...
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... NXP Semiconductors Table 189. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1) Bit Symbol 7:0 DLLSB 31:8 - Table 190. UART Divisor Latch MSB Register (U0DLM - address 0x4000 8004 when Bit Symbol 7:0 DLMSB 31:8 - 11.6.4 UART Interrupt Enable Register (U0IER - 0x4000 8004, when DLAB = 0) The U0IER is used to enable the four UART interrupt sources ...
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... NXP Semiconductors 11.6.5 UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only) U0IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during a U0IIR access interrupt occurs during a U0IIR access, the interrupt is recorded for the next U0IIR access. ...
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... NXP Semiconductors The UART RDA interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the trigger level defined in U0FCR7:6 and is reset when the UART Rx FIFO depth falls below the trigger level ...
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... NXP Semiconductors initialization conditions implement a one character delay minus the stop bit whenever THRE = 1 and there have not been at least two characters in the U0THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to U0THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART THR FIFO has held two or more characters at one time and currently, the U0THR is empty ...
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... NXP Semiconductors Table 195. UART Line Control Register (U0LCR - address 0x4000 800C) bit description Bit Symbol Value Description 2 Stop Bit Select 3 Parity Enable 5:4 Parity Select 6 Break Control 7 Divisor Latch Access Bit (DLAB) 31 11.6.8 UART Modem Control Register The U0MCR enables the modem loopback mode and controls the modem output signals. ...
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... NXP Semiconductors Table 196. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description Bit Symbol 4 Loopback Mode Select RTSen 7 CTSen 11.6.8.1 Auto-flow control If auto-RTS mode is enabled the UART‘s receiver FIFO hardware controls the RTS output of the UART. If the auto-CTS mode is enabled the UART‘s U0TSR hardware will only start transmitting if the CTS input signal is asserted ...
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... NXP Semiconductors UART Rx start byte N stop RTS pin UART Rx FIFO read UART Rx N-1 FIFO level Fig 16. Auto-RTS Functional Timing 11.6.8.1.2 Auto-CTS The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled, the transmitter circuitry in the U0TSR module checks CTS input before sending the next data byte ...
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... NXP Semiconductors UART TX start bits0..7 stop CTS pin Fig 17. Auto-CTS Functional Timing While starting transmission of the initial character, the CTS signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS is de-asserted (high). As soon as CTS gets de-asserted, transmission resumes and a start bit is sent followed by the data bits of the next character ...
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... NXP Semiconductors Table 198. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit Bit Symbol 3 Framing Error (FE) 4 Break Interrupt (BI) 5 Transmitte r Holding Register Empty (THRE) 6 Transmitte r Empty (TEMT) 7 Error in RX FIFO (RXFE) 31 11.6.10 UART Modem Status Register The U0MSR is a read-only register that provides status information on the modem input signals ...
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... NXP Semiconductors Table 199. UART Modem Status Register (U0MSR - address 0x4000 8018) bit description Bit Symbol Value Description 0 Delta CTS 1 Delta DSR 2 Trailing Edge RI 3 Delta DCD 4 CTS 5 DSR DCD 31 11.6.11 UART Scratch Pad Register (U0SCR - 0x4000 801C) The U0SCR has no effect on the UART operation. This register can be written and/or read at user’ ...
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... NXP Semiconductors Table 201. Auto-baud Control Register (U0ACR - address 0x4000 8020) bit description Bit Symbol 0 Start 1 Mode 2 AutoRestart 0 7 ABEOIntClr 9 ABTOIntClr 31:10 - 11.6.13 Auto-baud The UART auto-baud function can be used to measure the incoming baud rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U0DLM and U0DLL accordingly ...
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... NXP Semiconductors The U0ACR AutoRestart bit can be used to automatically restart baud rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set, the rate measurement will restart at the next falling edge of the UART Rx pin. The auto-baud function can generate two interrupts. ...
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... NXP Semiconductors 6. The rate counter is loaded into U0DLM/U0DLL and the baud rate will be switched to normal operation. After setting the U0DLM/U0DLL, the end of auto-baud interrupt U0IIR ABEOInt will be set, if enabled. The U0RSR will now continue receiving the remaining bits of the ”A/a" character. ...
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... NXP Semiconductors Table 202. UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description Bit Function 3:0 DIVADDVAL 7:4 MULVAL 31:8 - This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature ...
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... NXP Semiconductors Pick another FR the range [1.1, 1.9] Fig 19. Algorithm for setting UART dividers UM10375 User manual Calculating UART baudrate (BR) PCLK PCLK/(16 x BR) est est integer 1.5 est from est DL = Int(PCLK/( est FR = PCLK/( est False 1.1 < FR < 1.9? est DIVADDVAL = table(FR ...
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... NXP Semiconductors Table 203. Fractional Divider setting look-up table FR DivAddVal/ MulVal 1.000 0/1 1.067 1/15 1.071 1/14 1.077 1/13 1.083 1/12 1.091 1/11 1.100 1/10 1.111 1/9 1.125 1/8 1.133 2/15 1.143 1/7 1.154 2/13 1.167 1/6 1.182 2/11 1.200 1/5 1 ...
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... NXP Semiconductors Although Table 204 control strongly suggested to let UART hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. Table 204 Table 204. UART Transmit Enable Register (U0TER - address 0x4000 8030) bit description ...
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... NXP Semiconductors Table 205. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit Bit Symbol 31:6 - 11.6.18 UART RS-485 Address Match register (U0RS485ADRMATCH - 0x4000 8050) The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 206. UART RS-485 Address Match register (U0RS485ADRMATCH - address ...
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... NXP Semiconductors RS-485/EIA-485 Normal Multidrop Mode (NMM) Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘ ...
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... NXP Semiconductors The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de-assertion of RTS. This delay time can be programmed in the 8-bit RS485DLY register. The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may be used ...
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... NXP Semiconductors U0INTR Fig 20. UART block diagram UM10375 User manual INTERRUPT U0IER U0IIR U0SCR PA[2:0] PSEL PSTB PWRITE APB PD[7:0] INTERFACE AR MR PCLK All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 July 2010 UM10375 Chapter 11: LPC13xx UART U0TX NTXRDY ...
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UM10375 Chapter 12: LPC13xx I2C-bus controller Rev. 2 — 7 July 2010 12.1 How to read this chapter 2 The I C-bus block is identical for all LPC13xx parts. 12.2 Basic configuration 2 The I C-bus interface is configured using ...
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... I C-bus Fig 21 12.5 Fast-mode Plus Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I products which NXP Semiconductors is now providing. In order to use Fast-Mode Plus, the I IOCONFIG register block, see 400 kHz and MHz may be selected. UM10375 User manual 2 pull-up ...
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... NXP Semiconductors 12.6 Pin description Table 208. I Pin SDA SCL 2 The I C-bus pins must be configured through the IOCON_PIO0_4 IOCON_PIO0_5 these modes, the C-bus specification. 12.7 Clocking and power control The clock to the I Figure 3). This clock can be disabled through bit 5 in the SYSAHBCLKCTRL register (Table 23) for power savings ...
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... NXP Semiconductors 2 Table 209. Register overview (base address 0x4000 0000) Name Access Address offset I2C0ADR1 R/W 0x020 I2C0ADR2 R/W 0x024 I2C0ADR3 R/W 0x028 I2C0DATA_ RO 0x02C BUFFER I2C0MASK0 R/W 0x030 I2C0MASK1 R/W 0x034 I2C0MASK2 R/W 0x038 I2C0MASK3 R/W 0x03C [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. ...
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... NXP Semiconductors 2 I2EN I C Interface Enable. When I2EN is 1, the I cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I interface is disabled. When I2EN is “0”, the SDA and SCL input signals are ignored, the I addressed” slave state, and the STO bit is forced to “0”. ...
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... NXP Semiconductors 2. The General Call address has been received while the General Call bit (GC) in I2ADR is set data byte has been received while the data byte has been received while the I The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA ...
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... NXP Semiconductors Any of these registers which contain the bit 00x will be disabled and will not match any address on the bus. The slave address register will be cleared to this disabled state on reset. See also Table 213. I Bit Symbol Description 0 GC 7:1 Address The I ...
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... NXP Semiconductors Table 216. I2SCLL + I2SCLH values for selected mode I C bit frequency Standard mode 100 kHz Fast-mode 400 kHz Fast-mode Plus 1 MHz I2SCLL and I2SCLH values should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I ...
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... NXP Semiconductors Table 218. I Bit Symbol 0 MM_ENA 1 ENA_SCL 2 MATCH_ALL 31:3 - [1] When the ENA_SCL bit is cleared and the I time becomes important. To give the part more time to respond DATA _BUFFER register is used time. Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if the module is NOT in monitor mode) ...
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... NXP Semiconductors Subsequent to an address-match detection, interrupts will be generated after each data byte is received for a slave-write transfer, or after each byte that the module “thinks” it has transmitted for a slave-read transfer. In this second case, the data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master ...
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... NXP Semiconductors Although the DATA_BUFFER register is primarily intended for use in monitor mode with the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of operation. Table 220. I Bit Symbol 7:0 Data 31 12.8. Mask registers (I2C0MASK[ 0x4000 00[30, 34, 38, 3C]) The four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘ ...