LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 266

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 261: Capture Control Register (TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address
UM10375
User manual
Bit
0
1
2
31:3
Symbol
CAP0RE 1
CAP0FE
CAP0I
-
0x4001 8028) bit description
15.8.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
15.8.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001
15.8.8 Capture Control Register (TMR32B0CCR and TMR32B1CCR)
15.8.9 Capture Register (TMR32B0CR0 - address 0x4001 402C and
Value Description
0
1
0
1
0
4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Timer Counter when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
TMR32B1CR0 - address 0x4001 802C)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules
controlled PWM outputs” on page
Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
This feature is disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 15: LPC13xx 32-bit timer/counters (CT32B0/1)
271).
(Section 15.8.13 “Rules for single edge
UM10375
© NXP B.V. 2010. All rights reserved.
268 of 333
Reset
value
0
0
0
NA