LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 317

IC MCU 32BIT 32KB FLASH 48LQFP

LPC1313FBD48,151

Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Datasheets

Specifications of LPC1313FBD48,151

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151

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NXP Semiconductors
21.3 Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. USB PLL control register (USBPLLCTRL, address
Table 11. USB PLL status register (USBPLLSTAT, address
Table 12. System oscillator control register (SYSOSCCTRL,
Table 13. Watchdog oscillator control register
Table 14. Internal resonant crystal control register
Table 15. System reset status register (SYSRESSTAT,
Table 16. System PLL clock source select register
Table 17. System PLL clock source update enable register
Table 18. USB PLL clock source select register
Table 19. USB PLL clock source update enable register
Table 20. Main clock source select register (MAINCLKSEL,
Table 21. Main clock source update enable register
Table 22. System AHB clock divider register
Table 23. System AHB clock control register
Table 24. SSP clock divider register (SSPCLKDIV, address
Table 25. UART clock divider register (UARTCLKDIV,
UM10375
User manual
Ordering options for the LPC13xx parts . . . . . . .6
LPC13xx memory configuration . . . . . . . . . . . . .8
USB related registers and register bits reserved
for LPC1311/13. . . . . . . . . . . . . . . . . . . . . . . . .10
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .14
System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .16
System PLL control register (SYSPLLCTRL,
address 0x4004 8008) bit description . . . . . . .17
System PLL status register (SYSPLLSTAT,
address 0x4004 800C) bit description . . . . . . .17
0x4004 8010) bit description . . . . . . . . . . . . . .17
0x4004 8014) bit description . . . . . . . . . . . . . .18
address 0x4004 8020) bit description. . . . . . . .19
(WDTOSCCTRL, address 0x4004 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
(IRCCTRL, address 0x4004 8028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
address 0x4004 8030) bit description. . . . . . . .21
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(SYSPLLCLKUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(USBPLLCLKSEL, address 0x4004 8048) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(USBPLLCLKLUEN, address 0x4004 804C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
address 0x4004 8070) bit description. . . . . . . .23
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
(SYSAHBCLKDIV, address 0x4004 8078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description
0x4004 8094) bit description . . . . . . . . . . . . . .26
. . . . . . . . . . . . . . . . . . . . . . . . . . .24
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Table 26. TRACECLKDIV clock divider register
Table 27. SYSTICK clock divider register
Table 28. USB clock source select register (USBCLKSEL,
Table 29. USB clock source update enable register
Table 30. USB clock divider register (USBCLKDIV, address
Table 31. WDT clock source select register (WDTCLKSEL,
Table 32. WDT clock source update enable register
Table 33. WDT clock divider register (WDTCLKDIV, address
Table 34. CLKOUT clock source select register
Table 35. CLKOUT clock source update enable register
Table 36. CLKOUT clock divider registers (CLKOUTDIV,
Table 37. POR captured PIO status registers 0
Table 38. POR captured PIO status registers 1
Table 39. BOD control register (BODCTRL, address 0x4004
Table 40. System tick timer calibration register
Table 41. Start logic edge control register 0 (STARTAPRP0,
Table 42. Start logic signal enable register 0 (STARTERP0,
Table 43. Start logic reset register 0 (STARTRSRP0CLR,
Table 44. Start logic status register 0 (STARTSRP0,
Table 45. Start logic edge control register 1 (STARTAPRP1,
Table 46. Start logic signal enable register 1 (STARTERP1,
Table 47. Start logic reset register 1 (STARTRSRP1CLR,
Table 48. Start logic signal status register 1 (STARTSRP1,
Chapter 21: LPC13xx Supplementary information
address 0x4004 8098) bit description . . . . . . . 26
(TRACECLKDIV, address 0x4004 80AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(SYSTICKCLKDIV, address 0x4004 80B0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
address 0x4004 80C0) bit description . . . . . . . 28
(USBCLKUEN, address 0x4004 80C4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
0x4004 80C8) bit description . . . . . . . . . . . . . . 28
address 0x4004 80D0) bit description . . . . . . . 29
(WDTCLKUEN, address 0x4004 80D4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
0x4004 80D8) bit description . . . . . . . . . . . . . . 29
(CLKOUTCLKSEL, address 0x4004 80E0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
(CLKOUTUEN, address 0x4004 80E4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
address 0x4004 80E8) bit description . . . . . . . 30
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
(PIOPORCAP1, address 0x4004 8104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8150) bit description. . . . . . . . . . . . . . . . . . . . . 31
(SYSTCKCAL, address 0x4004 8158) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
address 0x4004 8200) bit description . . . . . . 32
address 0x4004 8204) bit description . . . . . . 33
address 0x4004 8208) bit description . . . . . . 34
address 0x4004 820C) bit description . . . . . . 35
address 0x4004 8210) bit description . . . . . . 35
address 0x4004 8214) bit description . . . . . . 36
address 0x4004 8218) bit description . . . . . . 37
address 0x4004 821C) bit description . . . . . . 37
UM10375
© NXP B.V. 2010. All rights reserved.
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