LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 185

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
UM10375
User manual
11.6.17 UART RS485 Control register (U0RS485CTRL - 0x4000 804C)
Although
control, it is strongly suggested to let UART hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
Table 204
Table 204. UART Transmit Enable Register (U0TER - address 0x4000 8030) bit description
The U0RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
Table 205. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit
Bit
6:0
7
31:8 -
Bit
0
1
2
3
4
5
Symbol
NMMEN
RXDIS
AADEN
SEL
DCTRL
OINV
Symbol
-
TXEN
Table 204
describes how to use TXEn bit in order to achieve software flow control.
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
When this bit is 1, as it is after a Reset, data written to the THR
is output on the TXD pin as soon as any preceding data has
been sent. If this bit cleared to 0 while a character is being sent,
the transmission of that character is completed, but no further
characters are sent until this bit is set again. In other words, a 0
in this bit blocks the transfer of characters from the THR or TX
FIFO into the transmit shift register. Software can clear this bit
when it detects that the a hardware-handshaking TX-permit
signal (CTS) has gone false, or with software handshaking,
when it receives an XOFF character (DC3). Software can set
this bit again when it detects that the TX-permit signal has gone
true, or when it receives an XON (DC1) character.
Reserved
Value
0
1
0
1
0
1
0
1
0
1
describes how to use TxEn bit in order to achieve hardware flow
Rev. 2 — 7 July 2010
Description
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is disabled.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is enabled. In this mode, an address is detected
when a received byte causes the UART to set the
parity error and generate an interrupt.
The receiver is enabled.
The receiver is disabled.
Auto Address Detect (AAD) is disabled.
Auto Address Detect (AAD) is enabled.
If direction control is enabled (bit DCTRL = 1), pin
RTS is used for direction control.
If direction control is enabled (bit DCTRL = 1), pin
DTR is used for direction control.
Disable Auto Direction Control.
Enable Auto Direction Control.
This bit reverses the polarity of the direction
control signal on the RTS (or DTR) pin.
Chapter 11: LPC13xx UART
UM10375
© NXP B.V. 2010. All rights reserved.
Reset Value
NA
1
-
Reset
value
0
0
0
0
0
0
187 of 333