LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 55
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
MAXIM
Quantity:
1 560
Company:
Part Number:
LPC1313FBD48,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
5.6 Register description
Table 62.
UM10375
User manual
Name
ISER0
ISER1
ICER0
ICER1
ISPR0
ISPR1
ICPR0
ICPR1
IABR0
IABR1
IPR0
IPR1
IPR2
IPR3
IPR4
IPR5
IPR6
IPR7
IPR8
RW
RW
RW
Access Address
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
Register overview: NVIC (base address 0xE000 E000)
0x100
0x104
0x184
offset
0x180
0x200
0x204
0x280
0x284
0x300
0x304
0x400
0x404
0x408
0x40C
0x410
0x414
0x418
0x41C
0x420
The following table summarizes the registers in the NVIC as implemented in the LPC13xx.
The Cortex-M3 User Guide provides a functional description of the NVIC.
Description
Interrupt Set-Enable Register 0. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions.
Interrupt Set-Enable Register 1. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions.
Interrupt Clear-Enable Register 0. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions.
Interrupt Clear-Enable Register 1. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions.
Interrupt Set-Pending Register 0. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions.
Interrupt Set-Pending Register 1. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions.
Interrupt Clear-Pending Register 0. This register allows changing the interrupt
state to not pending and reading back the interrupt pending state for specific
peripheral functions.
Interrupt Clear-Pending Register 1. This register allows changing the interrupt
Interrupt Priority Registers 0. This register allows assigning a priority to each
state to not pending and reading back the interrupt pending state for specific
peripheral functions.
Interrupt Active Bit Register 0. This register allows reading the current interrupt
active state for specific peripheral functions.
Interrupt Active Bit Register 1. This register allows reading the current interrupt
active state for specific peripheral functions.
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 1 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 2. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 3. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 4. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 5. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 6. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 7. This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
Interrupt Priority Registers 8 This register allows assigning a priority to each
interrupt. Each register contains the 5-bit priority fields for 4 interrupts.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 5: LPC13xx Interrupt controller
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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