LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 194
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
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UM10375
User manual
I2EN I
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I
I
STA is the START flag. Setting this bit causes the I
transmit a START condition or transmit a Repeated START condition if it is already in
master mode.
When STA is 1 and the I
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I
already in master mode and data has been transmitted or received, it transmits a
Repeated START condition. STA may be set at any time, including when the I
is in an addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is
0, no START condition or Repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
interface is in master mode, and transmits a START condition thereafter. If the I
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
2
1. The address in the Slave Address Register has been received.
C-bus status is lost. The AA flag should be used instead.
2
C Interface Enable. When I2EN is 1, the I
2
C Interrupt Flag. This bit is set when the I
All information provided in this document is subject to legal disclaimers.
2
Rev. 2 — 7 July 2010
C interface is not already in master mode, it enters master mode,
Chapter 12: LPC13xx I2C-bus controller
2
C interface is enabled. I2EN can be
2
2
C interface to transmit a STOP
C interface to enter master mode and
2
2
C-bus since, when I2EN is reset, the
C state changes. However, entering
2
C-bus. When the bus detects
2
C block is in the “not
UM10375
© NXP B.V. 2010. All rights reserved.
2
C interface is
2
C-bus if it the
2
C interface
2
C
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2
C
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