LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 222

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 232. Miscellaneous States
UM10375
User manual
Status
Code
(I2CSTAT)
0xF8
0x00
12.11.6.1 Simultaneous Repeated START conditions from two masters
Status of the I
and hardware
No relevant state
information available;
SI = 0.
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
to enter an undefined
state.
12.11.6 Some special cases
2
causes the I
clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
The I
during a serial transfer:
A Repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
Repeated START condition (see
either master since they were both transmitting the same data.
If the I
a Repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
C block
•
•
•
•
•
2
C-bus
Simultaneous Repeated START conditions from two masters
Data transfer after loss of arbitration
Forced access to the I
I
Bus error
2
2
C-bus obstructed by a LOW level on SCL or SDA
C hardware has facilities to handle the following special cases that may occur
2
C hardware detects a Repeated START condition on the I
Application software response
To/From I2DAT
No I2DAT action
No I2DAT action
2
C block to enter the “not addressed” slave mode (a defined state) and to
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
2
C-bus
To I2CON
STA STO SI
0
No I2CON action
Figure
1
0
34). Until this occurs, arbitration is not lost by
AA
X
Chapter 12: LPC13xx I2C-bus controller
Next action taken by I
Wait or proceed current transfer.
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
block is switched to the not addressed
SLV mode. STO is reset.
2
C-bus before generating
UM10375
© NXP B.V. 2010. All rights reserved.
2
C hardware
2
224 of 333
C block
2
C