LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 44
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC1313FBD48,151
Manufacturer Part Number
LPC1313FBD48,151
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1313FBD48,151
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
42
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
OM11041
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
LPC1000
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
8KB
# I/os (max)
42
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
LPC1000
Maximum Speed
72 MHz
Number Of Programmable I/os
42
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4914
935289651151
935289651151
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UM10375
User manual
3.8.3.3 Wake-up from Deep-sleep mode
3.8.4.1 Power configuration in Deep power-down mode
3.8.4.2 Programming Deep power-down mode
3.8.4 Deep power-down mode
The microcontroller can wake up from Deep-sleep mode in the following ways:
Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency
determines the wake-up time causing the wake-up time to be longer than waking up with
the IRC.
In Deep power-down mode, power and clocks are shut off to the entire chip with the
exception of the WAKEUP pin. The Deep power-down mode is controlled by the PMU
(see
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in the general purpose registers of
the PMU block.
All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals are powered down. Only the WAKEUP pin is powered.
The following steps must be performed to enter Deep power-down mode:
1. Pull the WAKEUP pin externally HIGH.
2. Write one to the DPDEN bit in the PCON register (see
3. Store data to be retained in the general purpose registers
4. Write one to the SLEEPDEEP bit in the ARM Cortex-M3 SCR register.
5. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in
6. Use the ARM WFI instruction.
•
•
•
•
Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 and PIO1_0 can
be enabled as inputs to the start logic. The start logic does not require any clocks and
generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode.
Input signal to the start logic created by a match event on one of the general purpose
timer match outputs. The pin holding the timer match function must be enabled as
start logic input in the NVIC, the corresponding timer must be enabled in the
SYSAHBCLKCTRL register, and the watchdog oscillator must be running in
Deep-sleep mode (for details see
Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL
register
Reset from the watchdog timer. In this case, the watchdog oscillator must be running
in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in
the SYSAHBCLKCTRL register.
the PDRUNCFG register before entering Deep power-down mode.
Chapter
(Table
4).
All information provided in this document is subject to legal disclaimers.
39).
Rev. 2 — 7 July 2010
Section
Chapter 3: LPC13xx System configuration
3.9.3).
Table
(Table
58).
59).
UM10375
© NXP B.V. 2010. All rights reserved.
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