LPC1313FBD48,151 NXP Semiconductors, LPC1313FBD48,151 Datasheet - Page 320

• Manufacturer Part Number: LPC1313FBD48,151
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1313FBD48,151

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 42
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11041
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: LPC1000
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 72MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 42
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Number Of Programmable I/os: 42
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4918 - KIT DEV FOR LPC1313622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4914; 935289651151

NXP Semiconductors
Table 160. USB Command Code register (USBCmdCode -
Table 161. USB Command Data register (USBCmdData -
Table 162. USB Receive Data register (USBRxData -
Table 163. USB Transmit Data register (USBTxData -
Table 164. USB Receive Packet Length register
Table 165. USB Transmit Packet Length register
Table 166. USB Control register (USBCtrl - address 0x4002
Table 167. USB Device FIQ Select register (USBDevFIQSel
Table 168. SIE command code table. . . . . . . . . . . . . . . .141
Table 169. Device Set Address command description . .142
Table 170. Configure Device command description . . . .142
Table 171. Set Mode command description . . . . . . . . . .142
Table 172. Read interrupt Status byte 1 command
Table 173. Read interrupt Status byte 2 command
Table 174. Set Device Status command description . . . .144
Table 175. Get Error Code command description . . . . . .146
Table 176. Select Endpoint command description. . . . . .146
Table 177. Set Endpoint Status command description . .148
Table 178. Clear Buffer command description. . . . . . . . .149
Table 179. USB device information class structure . . . . .160
Table 180. Mass storage device information class
Table 181. Human interface device information class
Table 182. Standard descriptor . . . . . . . . . . . . . . . . . . . .162
Table 183. Mass storage descriptors. . . . . . . . . . . . . . . .163
Table 184. HID descriptors . . . . . . . . . . . . . . . . . . . . . . .164
Table 185. UART pin description . . . . . . . . . . . . . . . . . . .167
Table 186. Register overview: UART (base address: 0x4000
Table 187. UART Receiver Buffer Register (U0RBR -
Table 188. UART Transmitter Holding Register (U0THR -
Table 189. UART Divisor Latch LSB Register (U0DLL -
Table 190. UART Divisor Latch MSB Register (U0DLM -
Table 191. UART Interrupt Enable Register (U0IER -
Table 192. UART Interrupt Identification Register (U0IIR -
UM10375
User manual
address 0x4002 0010) bit description. . . . . . .135
address 0x4002 0014) bit description. . . . . . .136
address 0x4002 0018) bit description. . . . . . .136
address 0x4002 001C) bit description . . . . . .137
(USBRxPlen - address 0x4002 0020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .137
(USBTxPLen - address 0x4002 0024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .138
0028) bit description . . . . . . . . . . . . . . . . . . . .138
- address 0x4002 002C) bit description . . . . .139
description . . . . . . . . . . . . . . . . . . . . . . . . . . .143
description . . . . . . . . . . . . . . . . . . . . . . . . . . .143
structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
address 0x4000 8000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . .170
address 0x4000 8000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . .170
address 0x4000 8000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .171
address 0x4000 8004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .171
address 0x4000 8004 when DLAB = 0) bit
description
. . . . . . . . . . . . . . . . . . . . . . . . . .171
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Table 193. UART Interrupt Handling . . . . . . . . . . . . . . . . 173
Table 194. UART FIFO Control Register (U0FCR - address
Table 195. UART Line Control Register (U0LCR - address
Table 196. UART0 Modem Control Register (U0MCR -
Table 197. Modem status interrupt generation . . . . . . . . 177
Table 198. UART Line Status Register (U0LSR - address
Table 199. UART Modem Status Register (U0MSR - address
Table 200. UART Scratch Pad Register (U0SCR - address
Table 201. Auto-baud Control Register (U0ACR - address
Table 202. UART Fractional Divider Register (U0FDR -
Table 203. Fractional Divider setting look-up table . . . . . 186
Table 204. UART Transmit Enable Register (U0TER -
Table 205. UART RS485 Control register (U0RS485CTRL -
Table 206. UART RS-485 Address Match register
Table 207. UART RS-485 Delay value register
Table 208. I
Table 209. Register overview: I
Table 210. I
Table 211. I
Table 212. I
Table 213. I
Table 214. I
Table 215. I
Table 216. I2SCLL + I2SCLH values for selected I
Table 217. I
Table 218. I
Table 219. I
Table 220. I
Table 221. I
Chapter 21: LPC13xx Supplementary information
address 0x4004 8008, Read Only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 172
0x4000 8008, Write Only) bit description . . . . 174
0x4000 800C) bit description . . . . . . . . . . . . 174
address 0x4000 8010) bit description . . . . . . 175
0x4000 8014, Read Only) bit description . . . 178
0x4000 8018) bit description . . . . . . . . . . . . . 180
0x4000 8014) bit description . . . . . . . . . . . . . 180
0x4000 8020) bit description . . . . . . . . . . . . . 181
address 0x4000 8028) bit description . . . . . . 184
address 0x4000 8030) bit description . . . . . . 187
address 0x4000 804C) bit description . . . . . 187
(U0RS485ADRMATCH - address 0x4000 8050)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 188
(U0RS485DLY - address 0x4000 8054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
0x4000 0000) bit description . . . . . . . . . . . . . 195
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
0x4000 000C) bit description . . . . . . . . . . . . . 198
address 0x4000 0010) bit description . . . . . . 198
0x4000 0014) bit description . . . . . . . . . . . . . 198
values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
0x4000 0018) bit description . . . . . . . . . . . . . 199
- 0x4000 001C) bit description . . . . . . . . . . . . 200
0x4000 00[20, 24, 28]) bit description . . . . . . 201
0x4000 002C) bit description . . . . . . . . . . . . . 202
0x4000 00[30, 34, 38, 3C]) bit description . . . 202
2
2
2
2
2
2
2
2
2
2
2
2
C Status register (I2C0STAT - 0x4000 0004) bit
C-bus pin description . . . . . . . . . . . . . . . . . 194
C Control Set register (I2C0CONSET - address
C Data register (I2C0DAT - 0x4000 0008) bit
C Slave Address register 0 (I2C0ADR0-
C SCL HIGH Duty Cycle register (I2C0SCLH -
C SCL Low duty cycle register (I2C0SCLL -
C Control Clear register (I2C0CONCLR -
C Monitor mode control register (I2C0MMCTRL
C Slave Address registers (I2C0ADR[1, 2, 3]-
C Data buffer register (I2C0DATA_BUFFER -
C Mask registers (I2C0MASK[0, 1, 2, 3] -
2
C (base address 0x4000
UM10375
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C clock