MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 86

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4
4.6.8 Reset Processing Summary
4-44
CLKOUT
CYCLES
RESET
NOTES:
LOCK
To prevent write cycles in progress from being corrupted, a reset is recognized at the
end of a bus cycle, and not at an instruction boundary. Any processing in progress at
the time a reset occurs is aborted. After SIM reset control logic has synchronized an
internal or external reset request, it asserts the MSTRST signal.
The following events take place when MSTRST is asserted.
The following events take place when MSTRST is negated after assertion.
VCO
V DD
1. Internal start-up time.
2. SSP fetched.
3. PC fetched.
4. First instruction fetched.
BUS
A. Instruction execution is aborted.
B. The status register is initialized.
C. The vector base register is initialized to $000000.
A. The CPU32 samples the BKPT input.
B. The CPU32 fetches the reset vector:
C. The CPU32 fetches and begins decoding the first instruction to be executed.
BUS STATE
UNKNOWN
1. The T0 and T1 bits are cleared to disable tracing.
2. The S bit is set to establish supervisor privilege level.
3. The interrupt priority mask is set to $7, disabling all interrupts below priority
1. The first long word of the vector is loaded into the interrupt stack pointer.
2. The second long word of the vector is loaded into the program counter.
7.
Vectors can be fetched from internal RAM or from external ROM enabled by
the CSBOOT signal.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 4-16 Power-On Reset
SYSTEM INTEGRATION MODULE
CONTROL SIGNALS
THREE-STATED
ADDRESS AND
Go to: www.freescale.com
512 CLOCKS
10 CLOCKS
1
USER’S MANUAL
2
MC68331
3
32 POR TIM
4