MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 61

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.4.1.7 Function Codes
4.4.1.8 Data and Size Acknowledge Signals
4.4.1.9 Bus Error Signal
MC68331
USER’S MANUAL
The CPU generates function code output signals FC[2:0] to indicate the type of activity
occurring on the data or address bus. These signals can be considered address ex-
tensions that can be externally decoded to determine which of eight external address
spaces is accessed during a bus cycle.
Address space 7 is designated CPU space. CPU space is used for control information
not normally associated with read or write bus cycles. Function codes are valid while
AS is asserted.
Table 4-11 shows address space encoding.
The supervisor bit in the status register determines whether the CPU is operating in
supervisor or user mode. Addressing mode and the instruction being executed deter-
mine whether a memory access is to program or data space.
During normal bus transfers, external devices assert the data and size acknowledge
signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig-
nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the
signals indicate that an external device has successfully stored data and that the cycle
can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer
to 4.8 Chip Selects for more information.
The bus error signal BERR is asserted when a bus cycle is not properly terminated by
DSACK or AVEC assertion. BERR can also be asserted at the same time as DSACK,
provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Exception
Control Cycles for more information.
FC2
Freescale Semiconductor, Inc.
0
0
0
0
1
1
1
1
Table 4-11 Address Space Encoding
For More Information On This Product,
SIZ1
Table 4-10 Size Signal Encoding
0
1
1
0
FC1
SYSTEM INTEGRATION MODULE
0
0
1
1
0
0
1
1
Go to: www.freescale.com
FC0
0
1
0
1
0
1
0
1
SIZ0
1
0
1
0
Supervisor Program Space
Supervisor Data Space
User Program Space
User Data Space
Address Space
CPU Space
Reserved
Reserved
Reserved
Transfer Size
Long Word
3 Byte
Word
Byte
4-19
4