MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 157

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6.4.3.9 Internal Loop
6.5 QSM Initialization
MC68331
USER’S MANUAL
for initialization follows.
lows idle time between frames and eliminates idle time between transmissions. How-
ever, there is a loss of efficiency because of an additional bit-time per frame.
The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When
LOOPS is set, SCI transmitter output is fed back into the receive serial shifter. TXD is
asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
After reset, the QSM remains in an idle state until initialized. A general sequence guide
A. Global
B. Queued Serial Peripheral Interface
1. Configuration register (QSMCR)
2. Interrupt vector and interrupt level registers (QIVR and QILR)
3. Port data and data direction registers (PORTQS and DDRQS)
4. Assign pin functions by writing to the pin assignment register (PQSPAR)
1. Write appropriate values to QSPI command RAM.
2. QSPI control register zero (SPCR0)
3. QSPI control register one (SPCR1)
4. QSPI control register two (SPCR2)
5. QSPI control register three (SPCR3)
6. To enable the QSPI, set the SPE bit in SPCR1.
a. Write an interrupt arbitration priority value into the IARB field.
b. Clear the FREEZE and/or STOP bits for normal operation.
a. Write QSPI/SCI interrupt vector into QIVR.
b. Write QSPI (ILSPI) and SCI (ILSCI) interrupt priorities into QILR.
a. Write a data word to PORTQS.
b. Establish direction of QSM pins used for I/O by writing to DDRQS.
a. Write a transfer rate value into the BR field.
b. Determine clock phase (CPHA), and clock polarity (CPOL).
c. Determine number of bits to be transferred in a serial operation (BIT).
d. Select master or slave operating mode (MSTR).
e. Enable or disable wired-OR operation (WOMQ).
a. Establish a delay following serial transfer by writing to the DTL field.
b. Establish a delay before serial transfer by writing to the DSCKL field.
a. Write an initial queue pointer value into the NEWQP field.
b. Write a final queue pointer value into the ENDQP field.
c. Enable or disable queue wraparound (WREN).
d. Write wraparound address into the WRTO field.
e. Enable or disable QSPI flag interrupt (SPIFIE).
a. Enable or disable halt at end of queue (HALT).
b. Enable or disable halt and mode fault interrupts (HMIE).
c. Enable or disable loopback (LOOPQ).
Freescale Semiconductor, Inc.
For More Information On This Product,
QUEUED SERIAL MODULE
Go to: www.freescale.com
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