MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 211

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.1.2 — Status Register
T[1:0] — Trace Enable
S — Supervisor/User State
IP[2:0] — Interrupt Priority Mask
X — Extend Flag
N — Negative Flag
Z — Zero Flag
V — Overflow Flag
C — Carry Flag
MC68331
USER’S MANUAL
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The status register (SR) contains condition codes, an interrupt priority mask, and three
control bits. The condition codes are contained in the condition code register (CCR),
the lower byte of the SR. (The lower and upper bytes of the status register are also
referred to as the user and system bytes, respectively.) At the user privilege level, only
the CCR is available. At the supervisor level, software can access the full status reg-
ister.
The priority value in this field (0 to 7) is used to mask interrupts.
Used in multiple-precision arithmetic operations. In many instructions it is set to the
same value as the C bit.
Set when the MSB of a result register is set.
Set when all bits of a result register are zero.
Set when two's complement overflow occurs as the result of an operation.
Set when a carry or borrow occurs during an arithmetic operation. Also used during
shift and rotate instructions to facilitate multiple word operations.
RESET:
T[1:0]
00 = No tracing
01 = Trace on change of flow
10 = Trace on instruction execution
11 = Undefined; reserved
0 = CPU operates at user privilege level
1 = CPU operates at supervisor privilege level
14
0
13
S
1
12
0
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
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0
10
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Go to: www.freescale.com
REGISTER SUMMARY
IP
1
8
1
7
0
0
6
0
0
5
0
0
U
4
X
N
U
3
U
2
Z
V
U
1
0
C
U
D-3
D