MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 218

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D
D.2.13 TFLG1/TFLG2 — Timer Interrupt Flag Registers 1 and 2
I4/O5F — Input Capture 4/Output Compare 5 Flag
OCF[4:1] — Output Compare Flags
ICF[3:1] — Input Capture Flags
TOF — Timer Overflow Flag
PAOVF — Pulse Accumulator Overflow Flag
PAIF — Pulse Accumulator Flag
D.2.14 CFORC — Compare Force Register
FOC[5:1] — Force Output Compare
D-10
RESET:
I4/O5F
15
15
0
0
RESET:
These registers show condition flags that correspond to GPT events. If the corre-
sponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs.
When I4/O5 in PACTL is zero, this flag is set each time TCNT matches the TOC5 val-
ue in TI4/O5. When I4/O5 in PACTL is one, the flag is set each time a selected edge
is detected at the I4/O5 pin.
An output compare flag is set each time TCNT matches the corresponding TOC reg-
ister. OCF[4:1] correspond to OC[4:1].
A flag is set each time a selected edge is detected at the corresponding input capture
pin. ICF[3:1] correspond to IC[3:1].
This flag is set each time TCNT advances from a value of $FFFF to $0000.
This flag is set each time the pulse accumulator counter advances from a value of $FF
to $00.
In event counting mode, this flag is set when an active edge is detected on the PAI pin.
In gated time accumulation mode, it is set at the end of the timed period.
Setting a bit in CFORC causes a specific output on OC or PWM pins. PWMC sets
PWM operating conditions.
FOC[5:1] correspond to OC[5:1].
PWMC — PWM Control Register C
0 = Has no meaning.
1 = Causes pin action programmed for corresponding OC pin, but the OC flag is
0
14
0
not set.
FOC
0
0
OCF
0
0
11
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
10
0
0
10
0
FPWMA
Go to: www.freescale.com
9
0
REGISTER SUMMARY
ICF
0
FPWMB
8
0
8
0
PPROUT
TOF
7
0
7
0
6
0
0
6
0
PAOVF
PPR
5
0
0
PAIF
4
0
4
0
SFA
3
0
3
0
0
USER’S MANUAL
SFB
2
0
2
0
0
$YFF922
$YFF924
$YFF925
F1A
1
0
MC68331
1
0
0
F1B
0
0
0
0
0