MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 209

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.1 Central Processing Unit
MC68331
USER’S MANUAL
This appendix contains address maps, register diagrams, and bit/field definitions for
the MCU. More detailed information about register function is provided in the appro-
priate sections of the manual.
Except for central processing unit resources, information is presented in the intermod-
ule bus address order shown in Table D-1.
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping (MM) bit in the SIM configuration register
(SIMCR) determines where the control registers block is located in the system mem-
ory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when
MM = 1, register addresses range from $FFF000 to $FFFFFF.
In the module memory maps in this appendix, the “Access” column specifies which
registers are accessible at the supervisor privilege level only and which registers can
be assigned to either the supervisor or user privilege level.
CPU32 registers are not part of the module address map. The following diagram is a
functional representation of CPU resources.
Module
APPENDIX D REGISTER SUMMARY
QSM
GPT
SIM
Freescale Semiconductor, Inc.
For More Information On This Product,
Table D-1 Module Address Map
Go to: www.freescale.com
REGISTER SUMMARY
Size (Bytes)
128
512
64
Base Address
$YFFA00
$YFFC00
$YFF900
D-1
D