MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 243

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

LOOPQ — QSPI Loop Mode
HMIE — HALTA and MODF Interrupt Enable
HALT — Halt
SPIF — QSPI Finished Flag
MODF — Mode Fault Flag
HALTA — Halt Acknowledge Flag
CPTQP — Completed Queue Pointer
D.4.14 RR[0:F] — Receive Data RAM
D.4.15 TR[0:F] — Transmit Data RAM
MC68331
USER’S MANUAL
CPTQP points to the last command executed. It is updated when the current command
is complete. When the first command in a queue is executing, CPTQP contains either
the reset value ($0) or a pointer to the last command completed in the previous queue.
Data received by the QSPI is stored in this segment. The CPU32 reads this segment
to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-
vidual queue entry. The CPU can access the data using byte, word, or long-word ad-
dressing.
Data that is to be transmitted by the QSPI is stored in this segment. The CPU32 nor-
mally writes one word of data into this segment for each queue command to be exe-
cuted.
Information to be transmitted must be written to transmit data RAM in a right-justified
format. The QSPI cannot modify information in the transmit data RAM. The QSPI cop-
ies the information to its data serializer for transmission. Information remains in trans-
mit RAM until overwritten.
0 = Feedback path disabled
1 = Feedback path enabled
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
0 = Halt not enabled
1 = Halt enabled
0 = QSPI not finished
1 = QSPI finished
0 =Normal operation
1 =Another SPI node requested to become the network SPI master while the QSPI
0 = QSPI not halted
1 = QSPI halted
was enabled in master mode (SS input taken low).
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
REGISTER SUMMARY
$YFFD00–$YFFD0E
$YFFD20–$YFFD3E
D-35
D