MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 22

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

2
2.5 Conventions
2-6
Logic level one is the voltage that corresponds to a Boolean true (1) state.
Logic level zero is the voltage that corresponds to a Boolean false (0) state.
Set refers specifically to establishing logic level one on a bit or bits.
Clear refers specifically to establishing logic level zero on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal chang-
es from logic level zero to logic level one.
Negated means that an asserted signal changes logic state. An active low signal
changes from logic level zero to logic level one when negated, and an active high sig-
nal changes from logic level one to logic level zero.
SCCR[0:1] — SCI Control Registers [0:1]
TSTMSRA — Test Module Master Shift Register A
TSTMSRB — Test Module Master Shift Register B
SPCR[0:3] — QSPI Control Registers [0:3]
TMSK[1:2] — Timer Interrupt Mask Register [1:2]
TFLG[1:2] — Timer Interrupt Flag Registers [1:2]
TCTL[1:2] — Timer Control Registers [1:2]
TOC[1:4] — Timer Output Compare Registers [1:4]
SIMTRE — System Integration Test Register (ECLK)
TIC[1:3] — Timer Input Capture Registers [1:3]
SYNCR — Clock Synthesizer Control Register
RR[0:F] — QSM Receive Data RAM
SYPCR — System Protection Control Register
QTEST — QSM Test Register
TR[0:F] — QSM Transmit Data RAM
TSTRC — Test Module Repetition Count Register
TSTSC — Test Module Shift Count Register
SIMCR — SIM Module Configuration Register
SIMTR — System Integration Test Register
TI4/O5 — Timer Input Capture 4/Output Compare 5 Register
SWSR — Software Watchdog Service Register
SCDR — SCI Data Register
SCSR — SCI Status Register
SPSR — QSPI Status Register
TCNT — Timer Counter Register
RSR — Reset Status Register
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NOMENCLATURE
USER’S MANUAL
MC68331