MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 186

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

A
A-10
Num
14A
14B
27A
29A
30A
39A
46A
47A
47B
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
30
31
33
35
37
39
46
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
AS, CS Width Asserted
DS, CS Width Asserted (Write)
AS, CS Width Asserted (Fast Write Cycle)
AS, DS, CS Width Negated
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
Clock High to R/W Low
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
Data Out Valid to Negating Edge of AS, CS
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time)
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
DS, CS Negated to Data In Invalid (Data In Hold)
DS, CS Negated to Data In High Impedance
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLKOUT Low to Data In High Impedance
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time
Mode Select Hold Time
RESET Assertion Time
RESET Rise Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
Table A-6a 20.97 MHz AC Timing, (Continued)
13,14
(V
DD
Freescale Semiconductor, Inc.
12
Characteristic
and V
For More Information On This Product,
6
ELECTRICAL CHARACTERISTICS
DDSYN
Go to: www.freescale.com
= 5.0 Vdc
9
7
7, 8
11
7
5%, V
7
10
SS
= 0 Vdc, T
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BRAGA
t
t
t
t
t
t
t
t
DVASN
t
t
CLBAN
t
SCLDD
SCLDS
SCLDH
t
t
t
t
SWAW
SWDW
SNDOI
BELCL
t
t
t
t
t
t
t
RWAS
t
HRPW
SNRN
CHRH
CHDO
SNDN
GAGN
t
DOCH
CHDH
RADC
BNHN
t
t
CHSZ
CHRL
RAAA
RASA
DVSA
CLDH
DABA
BKST
BKHT
RSTA
RSTR
SWA
DICL
SNDI
SHDI
CLDI
DADI
RWA
AIHT
t
t
AIST
MSS
MSH
t
GH
GA
SN
A
= T
L
to T
Min
115
512
H
80
36
32
32
10
10
54
10
10
10
15
10
70
12
32
10
10
10
10
20
—
—
—
—
—
—
—
—
—
0
0
5
0
0
1
1
2
1
5
0
0
0
0
4
)
USER’S MANUAL
Max
47
23
23
23
60
48
72
46
23
30
23
23
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
MC68331
Unit
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc