MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 120

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5
5.10.2.2.1 External BKPT Signal
5.10.2.2.2 BGND Instruction
5.10.2.2.3 Double Bus Fault
5.10.2.2.4 Peripheral Breakpoints
5.10.2.3 Entering BDM
5-20
Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM
is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has
the same timing relationship to the data strobe trailing edge as does read cycle data.
There is no breakpoint acknowledge bus cycle when BDM is entered.
An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32
defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is dis-
abled, an illegal instruction trap is acknowledged.
The CPU32 normally treats a double bus fault, or two bus faults in succession, as a
catastrophic system error, and halts. When this condition occurs during initial system
debug (a fault in the reset logic), further debugging is impossible until the problem is
corrected. In BDM, the fault can be temporarily bypassed, so that the origin of the fault
can be isolated and eliminated.
CPU32 peripheral breakpoints are implemented in the same way as external break-
points — peripherals request breakpoints by asserting the BKPT signal. Consult the
appropriate peripheral user's manual for additional details on the generation of periph-
eral breakpoints.
When the processor detects a breakpoint or a double bus fault, or decodes a BGND
instruction, it suspends instruction execution and asserts the FREEZE output. This is
the first indication that the processor has entered BDM. Once FREEZE has been as-
serted, the CPU enables the serial communication hardware and awaits a command.
The CPU writes a unique value indicating the source of BDM transition into temporary
register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP
and determine the source (see Table 5-4) by issuing a read system register command
(RSREG). ATEMP is used in most debugger commands for temporary storage — it is
imperative that the RSREG command be the first command issued after transition into
BDM.
A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence
is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other
time will the processor write an odd value into this register.
*Special status word (SSW) is described in detail in the CPU32 Reference Manual (CPU32RM/AD).
Hardware Breakpoint
BGND Instruction
Double Bus Fault
Source
Table 5-4 Polling the BDM Entry Source
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ATEMP[31:16]
$0000
$0000
SSW*
ATEMP[15:0]
$FFFF
$0001
$0000
USER’S MANUAL
MC68331