MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 248

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D
D-40
ADDR[23:11]
DDRGP[7:0]
CSPA0[6:1]
CSPA1[4:0]
Mnemonic
DDQS[7:0]
EDGE[4:1]
CPROUT
CSBOOT
BMT[1:0]
CPR[2:0]
DDE[7:0]
FOC[5:1]
DDF[7:0]
FRZ[1:0]
FRZ[1:0]
FPWMA
FPWMB
ENDQP
FRZSW
CPTQP
DSACK
DSCKL
EXOFF
FRZBM
HALTA
BLKSZ
BITSE
CONT
CPHA
DSCK
AVEC
CPOL
BYTE
HALT
HMIE
BITS
EDIV
HME
BME
DTL
EXT
F1A
F1B
HLT
DT
FE
C
Table D-18 Register Bit and Field Mnemonics
Freescale Semiconductor, Inc.
For More Information On This Product,
Capture/Compare Clock Output Enable
HALTA and MODF Interrupt Enable
Timer Prescaler/PCLK Select Field
Force Logic Level One on PWMA
Force Logic Level One on PWMB
Length of Delay After Transfer
Bus Monitor External Enable
Input Capture Edge Control
Freeze Bus Monitor Enable
Completed Queue Pointer
Data Strobe Acknowledge
Upper/Lower Byte Option
Bits Per Transfer Enable
Freeze Software Enable
Force Output Compare
Halt Acknowledge Flag
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Boot ROM Chip Select
Port GP Data Direction
Port QS Data Direction
Ending Queue Pointer
Port E Data Direction
Port F Data Direction
Delay After Transfer
Force PWMA Value
Force PWMB Value
Halt Monitor Enable
Bus Monitor Timing
REGISTER SUMMARY
PCS to SCK Delay
Halt Monitor Reset
Autovector Enable
Delay Before SCK
ECLK Divide Rate
External Clock Off
Freeze Response
Bits Per Transfer
Chip-Select [6:1]
Chip-Select [4:0]
External Reset
Base Address
Clock Polarity
Framing Error
Clock Phase
Block Size
Carry Flag
Continue
Freeze1
Name
Halt
CSBAR[0:10], CSBARBT
CSBAR[0:10], CSBARBT
CSOR[0:10], CSORBT
CSOR[0:10], CSORBT
CSOR[0:10], CSORBT
Register Location
GPTMCR
CSPAR0
CSPAR1
CSPAR0
QSMCR
DDRGP
DDRQS
CFORC
CFORC
CFORC
CR[0:F]
SYPCR
SYPCR
CR[0:F]
CR[0:F]
CR[0:F]
SYNCR
SYPCR
SPCR0
SPCR0
SPCR0
TMSK2
TMSK2
SPCR1
SPCR1
SPCR2
SPCR3
SPCR3
SIMCR
PWMC
PWMC
SIMCR
SIMCR
TCTL2
DDRE
DDRF
SCSR
SPSR
SPSR
CCR
RSR
RSR
USER’S MANUAL
MC68331