MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 48

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4
4-6
Both writes must occur before time-out in the order listed, but any number of instruc-
tions can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) and soft-
ware watchdog timing (SWT) fields in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 4-3. System software can change SWP value.
The SWT field selects the divide ratio used to establish software watchdog time-out
period. Time-out period is given by the following equations.
or
Table 4-4 shows the ratio for each combination of SWP and SWT bits. When SWT[1:0]
are modified, a watchdog service sequence must be performed before the new time-
out period can take effect.
Figure 4-3 is a block diagram of the watchdog timer and the clock control for the pe-
riodic interrupt timer.
Table 4-3 MODCLK Pin and SWP Bit During Reset
Time-out Period
Freescale Semiconductor, Inc.
Table 4-4 Software Watchdog Ratio
For More Information On This Product,
Time-out Period
0 (External Clock)
1 (Internal Clock)
SYSTEM INTEGRATION MODULE
MODCLK
SWP
0
0
0
0
1
1
1
1
Go to: www.freescale.com
=
------------------------------------------------------------------------------------ -
EXTAL Frequency Divide Ratio
SWT
00
01
10
11
00
01
10
11
=
------------------------------------------------ -
EXTAL Frequency
Divide Ratio
1 ( 512)
0 ( 1)
SWP
Ratio
2
2
2
2
2
2
2
2
11
13
15
18
20
22
24
1
9
USER’S MANUAL
MC68331