MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 73

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68331
USER’S MANUAL
Retry Termination
Table 4-14 shows various combinations of control signal sequences and the resulting
bus cycle terminations.
To properly control termination of a bus cycle for a retry or a bus error condition,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the re-
quired setup time and hold time for both of them are met for the same falling edge of
the MCU clock. (Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for timing
requirements.) External circuitry that provides these signals must be designed with
these constraints in mind, or else the internal bus monitor must be used.
DSACK, BERR, and HALT may be negated after AS is negated.
HALT and BERR are asserted in lieu of, at the same time as, or before DSACK
(case 5) or after DSACK (case 6); BERR is negated at the same time or after
DSACK; HALT may be negated at the same time or after BERR.
NOTES:
Number
N
A
NA
X
S
Case
1
2
3
4
5
6
= The number of current even bus state (S2, S4, etc.).
= Signal is asserted in this bus state.
= Signal is not asserted in this state.
= Don't care.
= Signal was asserted in previous state and remains asserted in this state.
If DSACK or BERR remain asserted into S2 of the next bus cycle,
that cycle may be terminated prematurely.
Table 4-14 DSACK, BERR, and HALT Assertion Results
DSACK-
DSACK-
DSACK-
DSACK-
DSACK-
Control
DSACK
Signal
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
NA/A
NA/A
Asserted on
Rising Edge
A/S
A/S
NA
NA
NA
NA
NA
NA
NA
N
A
A
A
A
A
A
A
of State
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N + 2
NA
NA
NA
S
X
S
S
X
S
X
X
S
X
S
S
X
A
A
Normal termination.
Halt termination: normal cycle terminate and halt.
Continue when HALT is negated.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Retry termination: terminate and retry when HALT is
negated.
Retry termination: terminate and retry when HALT is
negated.
WARNING
Result
4-31
4