MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 110

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5
5.7 Privilege Levels
5.8 Instructions
5-10
The halted processing state is an indication of catastrophic hardware failure. For ex-
ample, if during the exception processing of a bus error another bus error occurs, the
processor assumes that the system is unusable and halts.
The background processing state is initiated by breakpoints, execution of special in-
structions, or a double bus fault. Background processing is enabled by pulling BKPT
low during RESET. Background processing allows interactive debugging of the sys-
tem via a simple serial interface.
The processor operates at one of two levels of privilege: user or supervisor. Not all in-
structions are permitted to execute at the user level, but all instructions are available
at the supervisor level. Effective use of privilege level can protect system resources
from uncontrolled access. The state of the S bit in the status register determines the
privilege level and whether the user stack pointer (USP) or supervisor stack pointer
(SSP) is used for stack operations.
The CPU32 instruction set is summarized in Table 5-1. The instruction set of the
CPU32 is very similar to that of the MC68020. Two new instructions have been added
to facilitate controller applications: low-power stop (LPSTOP) and table lookup and in-
terpolate (TBLS, TBLSN, TBLU, TBLUN).
The following MC68020 instructions are not implemented on the CPU32:
BFxxx
CALLM, RTM
CAS, CAS2
cpxxx
PACK, UNPK
Memory
The CPU32 traps on unimplemented instructions or illegal effective addressing
modes, allowing user-supplied code to emulate unimplemented capabilities or to de-
fine special purpose functions. However, Freescale reserves the right to use all current-
ly unimplemented instruction operation codes for future M68000 core enhancements.
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
— Call Module, Return Module
— Compare and Swap (Read-Modify-Write Instructions)
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
— Pack, Unpack BCD Instructions
— Memory Indirect Addressing Modes
Freescale Semiconductor, Inc.
BFFFO, BFINS, BFSET, BFTST)
cpSAVE, cpScc, cpTRAPcc)
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
USER’S MANUAL
MC68331