MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 231

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.3.25 CSBARBT — Chip Select Base Address Register Boot ROM
ADDR[23:11] — Base Address
BLKSZ — Block Size
D.3.26 CSORBT — Chip Select Option Register Boot ROM
MODE — Asynchronous Bus/Synchronous E-clock Mode
BYTE — Upper/Lower Byte Option
MC68331
USER’S MANUAL
MODE
ADDR
15
23
15
0
0
Each chip-select pin has an associated base address register. A base address is the
lowest address in the block of addresses enabled by a chip select. CSBARBT contains
the base address for selection of a bootstrap peripheral memory device. Bit and field
definition for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ.
This field sets the starting address of a particular address space.
This field determines the size of the block above the base address that is enabled by
the chip select.
Contain parameters that support bootstrap operations from peripheral memory devic-
es. Bit and field definitions for CSORBT and CSOR[0:10] are the same.
Synchronous mode cannot be used with internally generated autovectors.
The value in this field determines whether a select signal can be asserted.
RESET:
RESET:
CSBAR[0:10] — Chip Select Base Address Registers
CSOR[0:10] — Chip Select Option Registers
0 = Asynchronous mode selected
1 = Synchronous mode selected
ADDR
14
22
14
0
0
BYTE
ADDR
13
21
13
0
0
ADDR
BLKSZ[2:0]
12
20
12
0
0
R/W
000
001
010
011
100
101
110
111
Freescale Semiconductor, Inc.
ADDR
11
19
11
For More Information On This Product,
0
0
Table D-11 Block Size Encoding
ADDR
STRB
10
18
10
0
0
Go to: www.freescale.com
Block Size
REGISTER SUMMARY
ADDR
17
128 K
256 K
512 K
9
0
9
0
16 K
64 K
1 M
2 K
8 K
ADDR
16
8
0
0
DSACK
ADDR
15
7
0
0
Address Lines Compared
ADDR
14
6
0
6
0
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
ADDR
13
5
0
5
0
SPACE
ADDR
12
4
0
4
0
$YFFA4C–$YFFA74
$YFFA4E–$YFFA76
ADDR
11
3
0
3
0
IPL
2
0
0
BLKSZ
$YFFA4A
$YFFA48
0
1
0
AVEC
D-23
0
0
0
0
D