MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 242

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D
D.4.12 SPCR2 — QSPI Control Register 2
SPIFIE — SPI Finished Interrupt Enable
WREN — Wrap Enable
WRTO — Wrap To
ENDQP — Ending Queue Pointer
NEWQP — New Queue Pointer Value
D.4.13 SPCR3 — QSPI Control Register 3
D-34
SPIFIE
15
15
0
0
0
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. The CPU32 has read/write access to SPCR2, but the QSM has read ac-
cess only. SPCR2 is buffered. New SPCR2 values become effective only after com-
pletion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to
restart at the designated location. SPCR2 reads return the value of the register, not
the buffer.
This field contains the last QSPI queue address.
This field contains the first QSPI queue address.
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enables, and
the halt control bit. The CPU has read/write access to SPCR3, but the QSM has read
access only. SPCR3 must be initialized before QSPI operation begins. Writing a new
value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains infor-
mation concerning the current serial transmission. Only the QSPI can set bits in SPSR.
The CPU reads SPSR to obtain QSPI status information and writes it to clear status
flags.
RESET:
RESET:
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
0 = Wraparound mode disabled
1 = Wraparound mode enabled
0 = Wrap to pointer address $0
1 = Wrap to address in NEWQP
SPSR — QSPI Status Register
WREN
14
0
0
14
0
13
0
0
WRTO
13
0
12
0
0
12
0
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
0
11
0
LOOPQ
10
0
Go to: www.freescale.com
0
REGISTER SUMMARY
ENDQP
HMIE
9
0
0
HALT
8
0
8
0
SPIF
7
0
7
0
0
MODF
6
0
6
0
0
HALTA
5
0
0
5
0
4
0
0
4
0
0
3
0
3
0
USER’S MANUAL
0
NEWQP
0
CPTQP
$YFFC1C
$YFFC1E
$YFFC1F
0
MC68331
0
0
0
0
0