MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 72

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

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4.5.4.2 LPSTOP Broadcast Cycle
4.5.5 Bus Exception Control Cycles
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the STOP bits in each module configuration register or the SIM can turn off system
clocks after execution of the LPSTOP instruction. When the CPU executes LPSTOP,
the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of low-power
mode when either an interrupt of higher priority than the stored mask or a reset occurs.
Refer to 4.3.4 Low-Power Operation and SECTION 5 CENTRAL PROCESSING
UNIT for more information.
During an LPSTOP broadcast cycle, the CPU performs a CPU space write to address
$3FFFE. This write puts a copy of the interrupt mask value in the clock control logic.
The mask is encoded on the data bus as shown in Figure 4-13. The LPSTOP CPU
space cycle is shown externally (if the bus is available) as an indication to external de-
vices that the MCU is going into low-power stop mode. The SIM provides an internally
generated DSACK response to this cycle. The timing of this bus cycle is the same as
for a fast write cycle.
An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus error processing oc-
curs when bus cycles are not terminated in the expected manner. The internal bus
monitor can be used to generate BERR internally, causing a bus error exception to be
taken. Bus cycles can also be terminated by assertion of the external BERR or HALT
signal, or by assertion of the two signals simultaneously.
Acceptable bus cycle termination sequences are summarized as follows. The case
numbers refer to Table 4-14, which indicates the results of each type of bus cycle ter-
mination.
Normal Termination
Halt Termination
Bus Error Termination
DSACK is asserted; BERR and HALT remain negated (case 1).
HALT is asserted at the same time or before DSACK, and BERR remains negated
(case 2).
BERR is asserted in lieu of, at the same time as, or before DSACK (case 3), or after
DSACK (case 4), and HALT remains negated; BERR is negated at the same time
or after DSACK.
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Figure 4-13 LPSTOP Interrupt Mask Level
Freescale Semiconductor, Inc.
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For More Information On This Product,
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SYSTEM INTEGRATION MODULE
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Go to: www.freescale.com
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USER’S MANUAL
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IP MASK
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MC68331
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