MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 151

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6.4.1.2 Status Register
6.4.1.3 Data Register
6.4.2 SCI Pins
6.4.3 SCI Operation
MC68331
USER’S MANUAL
The SCI status register (SCSR) contains flags that show SCI operating conditions.
These flags are cleared either by SCI hardware or by a read/write sequence. In gen-
eral, flags are cleared by reading the SCSR, then reading (receiver status bits) or writ-
ing (transmitter status bits) the SCDR. A long-word read can consecutively access
both the SCSR and SCDR. This action clears receive status flag bits that were set at
the time of the read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the as-
serted status bits, but before the CPU has written or read the SCDR, the newly set sta-
tus bit is not cleared. The SCSR must be read again with the bit set, and the SCDR
must be written or read before the status bit is cleared.
Reading either byte of the SCSR causes all 16 bits to be accessed, and any status bit
already set in either byte is cleared on a subsequent read or write of the SCDR.
The SCDR contains two data registers at the same address. The RDR is a read-only
register that contains data received by the SCI serial interface. The data comes into
the receive serial shifter and is transferred to the RDR. The TDR is a write-only register
that contains data to be transmitted. The data is first written to the TDR, then trans-
ferred to the transmit serial shifter, where additional format bits are added before trans-
mission. R[7:0]/T[7:0] contain either the first eight data bits received when the SCDR
is read, or the first eight data bits to be transmitted when the SCDR is written. R8/T8
are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit
operation, they have no meaning or effect.
Two unidirectional pins, TXD (transmit data) and RXD (receive data), are associated
with the SCI. TXD can be used by the SCI or for general-purpose I/O. Function is as-
signed by the port QS pin assignment register (PQSPAR). The receive data (RXD) pin
is dedicated to the SCI. Table 6-4 shows SCI pin function.
SCI status flags in the SPSR support polled operation, or interrupt-driven operation
can be employed by the interrupt enable bits in SCCR1.
Transmit Data
Receive Data
Pin Names
Mnemonics
Freescale Semiconductor, Inc.
RXD
For More Information On This Product,
TXD
Table 6-4 SCI Pin Function
QUEUED SERIAL MODULE
Go to: www.freescale.com
Receiver Disabled
Receiver Enabled
Transmitter Disabled
Transmitter Enabled
Mode
Not Used
Serial Data Input to SCI
General-Purpose I/O
Serial Data Output from SCI
Function
6-25
6