MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 233

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.4 Queued Serial Module
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.4.1 QSMCR — QSM Configuration Register
STOP — Stop Enable
MC68331
USER’S MANUAL
STOP
QUEUE RAM
QUEUE RAM
QUEUE RAM
15
0
Table D-13 displays the QSM address map. The column labeled “Access” indicates
the privilege level at which the CPU must be operating to access the register. A des-
ignation of “S” indicates that supervisor access is required: a designation of “S/U” in-
dicates that the register can be programmed to the desired privilege level.
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
When STOP is set, the QSM enters low-power stop mode. System clock input to the
module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be
RESET:
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
0 = Normal QSM clock operation
1 = QSM clock operation stopped
S
S
S
FRZ1
14
0
FRZ0
13
0
$YFFC20–
$YFFD00–
$YFFD20–
$YFFD40–
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC1A
$YFFC1C
$YFFC1E
$YFFCFF
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFD1F
$YFFD3F
$YFFD4F
Address
12
0
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
0
Table D-13 QSM Address Map
15
PQS PIN ASSIGNMENT (PQSPAR)
QSM INTERRUPT LEVEL (QILR)
10
0
0
SPI CONTROL 3 (SPCR3)
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REGISTER SUMMARY
9
0
0
NOT USED
QSM MODULE CONFIGURATION (QSMCR)
8
0
0
SUPV
7
1
COMMAND RAM (CR[0:F])
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
TRANSMIT RAM (TR[0:F])
RECEIVE RAM (RR[0:F])
SCI STATUS (SCSR)
QSM TEST (QTEST)
SCI DATA (SCDR)
6
0
0
NOT USED
NOT USED
NOT USED
NOT USED
8 7
5
0
0
QSM INTERRUPT VECTOR (QIVR)
PQS DATA DIRECTION (DDRQS)
4
0
0
PQS DATA (PORTQS)
SPI STATUS (SPSR)
3
0
0
IARB
$YFFC00
0
D-25
0
0
0
D