MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 113

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68331
USER’S MANUAL
TBLSN/TBLUN
ORI to CCR
TBLS/TBLU
Instruction
ORI to SR
RESET
STOP
ROXR
SWAP
NEGX
SBCD
SUBQ
ROXL
SUBA
SUBX
TRAP
RTE
ROR
SUBI
NEG
NOP
NOT
PEA
ROL
RTD
RTR
RTS
SUB
ORI
Scc
OR
1
1
1
1
#<data>, <ea>
#<data>, CCR
#<data>, <ea>
#<data>, <ea>
Dym : Dyn, Dn
Dym : Dyn, Dn
– (An), – (An)
– (An), – (An)
#<data>, SR
#<data>, Dn
#<data>, Dn
#<data>, Dn
Table 5-1 Instruction Set Summary (Continued)
<ea>, Dn
Dn, <ea>
<ea>, Dn
Dn, <ea>
<ea>, An
<ea>, Dn
<ea>, Dn
#<data>,
#<data>
#<data>
Dn<ea>
Syntax
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
<ea>
#<d>
<ea>
none
none
none
none
none
Dn
Freescale Semiconductor, Inc.
For More Information On This Product,
Operand Size
CENTRAL PROCESSING UNIT
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
Go to: www.freescale.com
16, 32
none
none
none
none
none
none
16
16
32
16
16
16
16
16
88
16
16
8
If condition true, then destination bits are set to 1;
SSP – 2
SSP – 4
Destination
(SP)
(SP)
Destination – Source – X
else, destination bits are cleared to 0
Destination – Source
Destination – Source
Source; Destination
0 – Destination – X
Destination – Data
Destination – Data
(Temp * Dn [7 : 0]) / 256
restore stack according to format
Data; Destination
(SP)
0 – Destination
(Temp * Dn [7 : 0])
SP – 4
(Dym * 256) + Temp
(SP)
Destination
CCR; SP + 2
SSP; format/vector offset
SR; SP + 2
10
vector address
SSP; PC
Dyn – Dym
Dyn – Dym
Source; CCR
Dym + Temp
Data
Source; SR
Assert RESET line
– Source
SP + 4
PC + 2
SP + 4
PC; SP + 4 + d
Operation
PC; SP + 4
SP; <ea>
SR; STOP
10
Destination
(SSP); SR
SP; (SP)
SP;
– X
Destination
PC
SP
SP; (SP)
Temp
Temp
Destination
Destination
Destination
Destination
Destination
SR
Destination
Destination
SR
Dn
PC
Temp
Destination
SP
SP
Dn
Destination
Temp
SP
PC;
(SSP);
PC;
(SSP);
5-13
5