MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 34

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3
3.5 Intermodule Bus
3.6 System Memory Map
3.6.1 Internal Register Map
3.6.2 Address Space Maps
3-10
The intermodule bus (IMB) is a standardized bus developed to facilitate both design
and operation of modular microcontrollers. It contains circuitry to support exception
processing, address space partitioning, multiple interrupt levels, and vectored inter-
rupts. The standardized modules in the MCU communicate with one another and with
external components through the IMB. The IMB in the MCU uses 24 address and 16
data lines.
Figure 3-4, Figure 3-5, Figure 3-6, Figure 3-7, and Figure 3-8 are MCU memory
maps. Figure 3-4 shows IMB addresses of internal registers. Figure 3-5 through Fig-
ure 3-8 show system memory maps that use different external decoding schemes.
In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represent-
ed by Y determines the base address of MCU module control registers. In M68300 mi-
crocontrollers, Y is equal to M111, where M is the logic state of the module mapping
(MM) bit in the system integration module configuration register (SIMCR).
Figure 3-5 shows a single memory space. Function codes FC[2:0] are not decoded
externally so that separate user/supervisor or program/data spaces are not provided.
In Figure 3-6, FC2 is decoded, resulting in separate supervisor and user spaces.
FC[1:0] are not decoded, so that separate program and data spaces are not provided.
In Figure 3-7 and Figure 3-8, FC[2:0] are decoded, resulting in four separate memory
spaces: supervisor/program, supervisor/data, user/program and user/data.
All exception vectors are located in supervisor data space, except the reset vector,
which is located in supervisor program space. Only the initial reset vector is fixed in
the processor's memory map. Once initialization is complete, there are no fixed as-
signments. Since the vector base register (VBR) provides the base address of the vec-
tor table, the vector table can be located anywhere in memory. Refer to SECTION 5
CENTRAL PROCESSING UNIT for more information concerning memory manage-
ment, extended addressing, and exception processing. Refer to SECTION 4 SYSTEM
INTEGRATION MODULE for more information concerning function codes and ad-
dress space types.
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MC68331