MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 162

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7
7.3.4 Test Mode
7.4 Polled and Interrupt-Driven Operation
7.4.1 Polled Operation
7-4
Test mode is used during Freescale factory testing. The GPT has no dedicated test-
mode control register; all GPT testing is done under control of the system integration
module.
Normal GPT function can be polled or interrupt-driven. All GPT functions have an as-
sociated status flag and an associated interrupt. The timer interrupt flag registers
(TFLG1 and TFLG2) contain status flags used for polled and interrupt-driven opera-
tion. The timer mask registers (TMSK1 and TMSK2) contain interrupt control bits. Con-
trol routines can monitor GPT operation by polling the status registers. When an event
occurs, the control routine transfers control to a service routine that handles that event.
If interrupts are enabled for an event, the GPT requests interrupt service when the
event occurs. Using interrupts does not require continuously polling the status flags to
see if an event has taken place. However, status flags must be cleared after an inter-
rupt is serviced, in order to disable the interrupt request.
When an event occurs in the GPT, that event sets a status flag in TFLG1 or TFLG2.
The GPT sets the flags; they cannot be set by the CPU. TFLG1 and TFLG2 are 8-bit
registers that can be accessed individually or as one 16-bit register. The registers are
initialized to zero at reset. Table 7-1 shows status flag assignment.
For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2
in the same bit position. If a mask bit is set and an associated event occurs, a hardware
interrupt request is generated.
To re-enable a status flag after an event occurs, the status flags must be cleared. Sta-
tus registers are cleared in a particular sequence. The register must first be read for
set flags, then zeros must be written to the flags that are to be cleared. If a new event
occurs between the time that the register is read and the time that it is written, the as-
sociated flag is not cleared.
Mnemonic
PAOVF
I4/O5F
OC1F
OC2F
OC3F
OC4F
PAIF
Flag
IC1F
IC2F
IC3F
TOF
Freescale Semiconductor, Inc.
For More Information On This Product,
Assignment
Register
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG2
TFLG2
TFLG2
Table 7-1 GPT Status Flags
GENERAL-PURPOSE TIMER
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Input Capture 4/Output Compare 5
Pulse Accumulator Overflow
Pulse Accumulator Input
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 1
Input Capture 2
Input Capture 3
Timer Overflow
Source
USER’S MANUAL
MC68331