MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 224

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D
Y[5:0] — Frequency Control (Counter)
EDIV — ECLK Divide Rate
SLIMP — Limp Mode
SLOCK — Synthesizer Lock
RSTEN — Reset Enable
STSIM — Stop Mode System Integration Clock
STEXT — Stop Mode External Clock
D.3.4 RSR — Reset Status Register
EXT — External Reset
POW — Power-Up Reset
SW — Software Watchdog Reset
HLT — Halt Monitor Reset
D-16
15
The Y field is the initial value for the modulus 64 down counter in the synthesizer feed-
back loop. Values range from 0 to 63.
RSR contains a status bit for each reset source in the MCU. RSR is updated when the
MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple
sources assert reset signals at the same time, more than one bit in RSR may be set.
This register can be read at any time; a write has no effect.
Reset caused by an external signal.
Reset caused by the power-up reset circuit.
Reset caused by the software watchdog circuit.
Reset caused by the halt monitor.
0 = ECLK is system clock divided by 8
1 = ECLK is system clock divided by 16
0 = External crystal is VCO reference
1 = Loss of crystal reference
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency or system clock is external.
0 = Loss of reference causes the MCU to operate in limp mode.
1 = Loss of reference causes system reset.
0 = SIM clock driven by an external source and VCO off during low-power stop.
1 = SIM clock driven by VCO during low-power stop.
0 = CLKOUT held low during low-power stop.
1 = CLKOUT driven from SIM clock during low-power stop.
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
REGISTER SUMMARY
8
EXT
7
POW
6
SW
5
HLT
4
3
0
USER’S MANUAL
LOC
2
$YFFA07
SYS
1
MC68331
TST
0