MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 121

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.10.2.4 BDM Commands
5.10.2.5 Background Mode Registers
MC68331
USER’S MANUAL
Commands consist of one 16-bit operation word and can include one or more 16-bit
extension words. Each incoming word is read as it is assembled by the serial interface.
The microcode routine corresponding to a command is executed as soon as the com-
mand is complete. Result operands are loaded into the output shift register to be shift-
ed out as the next command is read. This process is repeated for each command until
the CPU returns to normal operating mode. Table 5-5 is a summary of background
mode commands.
BDM processing uses three special purpose registers to keep track of program context
during development. A description of each follows.
Read D/A Register
Write D/A Register
Read System Register
Write System Register
Read Memory Location
Write Memory Location
Dump Memory Block
Fill Memory Block
Resume Execution
Patch User Code
Reset Peripherals
No Operation
Command
Table 5-5 Background Mode Command Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
WDREG/WAREG The data operand is written to the specified ad-
RDREG/RAREG
Go to: www.freescale.com
Mnemonic
WSREG
RSREG
WRITE
DUMP
READ
CALL
NOP
FILL
RST
GO
Read the selected address or data register and
return the results via the serial interface.
dress or data register.
The specified system control register is read. All
registers that can be read in supervisor mode can
be read in background mode.
The operand data is written into the specified sys-
tem control register.
Read the sized data at the memory location spec-
ified by the long-word address. The source func-
tion code register (SFC) determines the address
space accessed.
Write the operand data to the memory location
specified by the long-word address. The destina-
tion function code (DFC) register determines the
address space accessed.
Used in conjunction with the READ command to
dump large blocks of memory. An initial READ is
executed to set up the starting address of the
block and retrieve the first result. Subsequent op-
erands are retrieved with the DUMP command.
Used in conjunction with the WRITE command to
fill large blocks of memory. An initial WRITE is ex-
ecuted to set up the starting address of the block
and supply the first operand. Subsequent oper-
ands are written with the FILL command.
The pipe is flushed and re-filled before resuming
instruction execution at the current PC.
Current program counter is stacked at the loca-
tion of the current stack pointer. Instruction exe-
cution begins at user patch code.
Asserts RESET for 512 clock cycles. The CPU is
not reset by this command. Synonymous with the
CPU RESET instruction.
NOP performs no operation and may be used as
a null command.
Description
5-21
5