MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 164

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7
7.5 Pin Descriptions
7.5.1 Input Capture Pins (IC[1:3])
7.5.2 Input Capture/Output Compare Pin (IC4/OC5)
7.5.3 Output Compare Pins (OC[1:4])
7-6
At reset, IVBA is initialized to $0. To enable interrupt-driven timer operation, the upper
nibble ($4–$F) of a user-defined vector number ($40–$FF) must be written to IVBA,
and interrupt handler routines must be located at the addresses pointed to by the cor-
responding vector. Note that IVBA must be written before GPT interrupts are enabled,
or the GPT could supply a vector number ($00 to $0F) that corresponds to an assigned
or reserved exception vector.
The internal GPT interrupt priority hierarchy is shown in Table 7-2. The lower the in-
terrupt source number, the higher the priority. A single GPT interrupt source can be
given priority over all other GPT interrupt sources by assigning the priority adjust field
(PAB) in the ICR a value equal to its source number.
Interrupt requests are asserted until associated status flags are cleared. Status flags
must be cleared in a particular sequence. The status register must first be read for set
flags, then zeros must be written to the flags that are to be cleared. If a new event oc-
curs between the time that the register is read and the time that it is written, the asso-
ciated flag is not cleared.
Refer to SECTION 5 CENTRAL PROCESSING UNIT and SECTION 4 SYSTEM IN-
TEGRATION MODULE for more information about exceptions and interrupts.
The GPT uses 12 pins. Each pin can perform more than one function. Descriptions of
GPT pins divided into functional groups follow.
Each of these pins is associated with a single GPT input capture function. Each pin
has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and
any pulse shorter than one system clock is ignored. Each pin has an associated 16-bit
capture register that holds the captured counter value. These pins can also be used
for general-purpose I/O. Refer to 7.8.2 Input Capture Functions for more informa-
tion.
This pin can be configured for use by either an input capture or an output compare
function. It has an associated 16-bit register that is used for holding either the input
capture value or the output match value. When used for input capture the pin has the
same hysteresis as other input capture pins. The pin can be used for general-purpose
I/O. Refer to 7.8.2 Input Capture Functions and 7.8.3 Output Compare Functions
for more information.
These pins are used for GPT output compare functions. Each pin has an associated
16-bit compare register and a 16-bit comparator. Pins OC2, OC3, and OC4 are asso-
ciated with a specific output compare function. The OC1 function can affect the output
of all compare pins. If the OC1 pin is not needed for an output compare function it can
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MC68331