MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 38

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3
3-14
$FFFFFF
$7FF000
$FF0000
$000000
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
Y = M111, where M is the state of the MM bit.
base register and the vector offset.
Figure 3-7 Supervisor Space (Separate Program/Data Space) Map
INTERNAL REGISTERS
INTERNAL REGISTERS
SUPERVISOR
SPACE
DATA
Freescale Semiconductor, Inc.
0080–00BC
00C0–00EB
00EC–00FC
0040–005C
0100–03FC
VECTOR
VECTOR
OFFSET
OFFSET
For More Information On This Product,
0000
0004
000C
001C
002C
003C
006C
006C
007C
0000
0004
0008
0010
0014
0018
0020
0024
0028
0030
0034
0038
0064
0068
0070
0074
0078
NUMBER
NUMBER
VECTOR
VECTOR
64–255
16–23
32–47
48–58
59–63
10
11
12
13
14
15
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
0
1
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RESERVED
RESERVED
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
QSM
GPT
SIM
OVERVIEW
IN SUPERVISOR PROGRAM SPACE
TAP INSTRUCTION VECTORS (0–15)
RESET — INITIAL STACK POINTER
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
RESET — INITIAL STACK POINTER
EXCEPTION VECTORS LOCATED
EXCEPTION VECTORS LOCATED
TRAPcc, TRAPV INSTRUCTIONS
IN SUPERVISOR DATA SPACE
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
(UNASSIGNED, RESERVED)
CHK, CHK2 INSTRUCTIONS
HARDWARE BREAKPOINT
USER-DEFINED VECTORS
ILLEGAL INSTRUCTION
SPURIOUS INTERRUPT
PRIVILEGE VIOLATION
RESET — INITIAL PC
LINE 1010 EMULATOR
LINE 1111 EMULATOR
RESET — INITIAL PC
ADDRESS ERROR
ZERO DIVISION
BUS ERROR
$YFF000
$YFF900
$YFF93F
$YFFA00
$YFFA7F
$YFFA80
$YFFAFF
$YFFC00
$YFFDFF
$YFFFFF
TRACE
$XX0000
$XX0004
$XX0000
$XX03FC
SUPERVISOR
PROGRAM
SPACE
USER’S MANUAL
331 SUPER P/D MAP
MC68331
$000000
$FFFFFF