MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 216

IC MCU 32BIT 25MHZ 132-PQFP

MC68331CEH25

Manufacturer Part Number
MC68331CEH25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68331CEH25

Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Controller Family/series
68K
No. Of I/o's
18
Cpu Speed
25MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
2
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Data Ram Size
80 B
Interface Type
QSPI, SCI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
18
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

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Company
Part Number
Manufacturer
Quantity
Price
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MC68331CEH25
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PANASONIC
Quantity:
2 000
Part Number:
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Manufacturer:
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D
D.2.8 TIC[1:3] — Input Capture Registers 1–3
D.2.9 TOC[1:4] — Output Compare Registers 1–4
D.2.10 TI4/O5 — Input Capture 4/Output Compare 5 Register
D.2.11 TCTL1/TCTL2 — Timer Control Registers 1 and 2
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
EDGE[4:1] — Input Capture Edge Control
D-8
OM5
15
0
The input capture registers are 16-bit read-only registers used to latch the value of
TCNT when a specified transition is detected on the corresponding input capture pin.
They are reset to $FFFF.
The 16-bit read/write output compare registers can be used as output waveform con-
trols or as elapsed time indicators. For output compare functions, they are written to a
desired match value and compared against TCNT to control specified pin actions.
They are reset to $FFFF.
This register serves either as input capture register 4 or output compare register 5, de-
pending on the state of I4/O5 in PACTL.
TCTL1 determines output compare mode and output logic level. TCTL2 determines
the type of input capture to be performed.
Each pair of bits specifies an action to be taken when output comparison is successful.
Each pair of bits configures input sensing logic for the corresponding input capture.
RESET:
OL5
14
0
OM4
13
0
OL4
12
0
OM/OL[5:2]
EDGE[4:1]
Freescale Semiconductor, Inc.
OM3
11
For More Information On This Product,
0
00
01
10
11
00
01
10
11
OL3
10
0
Go to: www.freescale.com
REGISTER SUMMARY
OM2
9
0
OL2
Capture on Any (Rising or Falling) Edge
8
0
Timer Disconnected from Output Logic
Clear OCx Output Line to zero
Capture on Falling Edge Only
Capture on Rising Edge Only
Set OCx Output Line to one
7
0
Toggle OCx Output Line
EDGE4
Capture Disabled
Configuration
Action Taken
6
0
5
0
EDGE3
4
0
$YFF914–$YFF91A
$YFF90E–$YFF912
3
0
EDGE2
USER’S MANUAL
2
0
$YFF91C
$YFF91E
1
0
MC68331
EDGE1
0
0

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