MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 169

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.8.1 Timer Counter
7.8.2 Input Capture Functions
MC68331
USER’S MANUAL
The timer counter (TCNT) is the key timing component in the capture/compare unit.
The timer counter is a 16-bit free-running counter that starts counting after the proces-
sor comes out of reset. The counter cannot be stopped during normal operation. After
reset, the GPT is configured to use the system clock divided by four as the input to the
counter. The prescaler divides the system clock and provides selectable input fre-
quencies. User software can configure the system to use one of seven prescaler out-
puts or an external clock.
The counter can be read any time without affecting its value. Because the GPT is in-
terfaced to the IMB and the IMB supports a 16-bit bus, a word read gives a coherent
value. If coherency is not needed, byte accesses can be made. The counter is set to
$0000 during reset and is normally a read-only register. In test mode and freeze mode,
any value can be written to the timer counter.
When the counter rolls over from $FFFF to $0000, the timer overflow flag (TOF) in tim-
er interrupt flag register 2 (TFLG2) is set. An interrupt can be enabled by setting the
corresponding interrupt enable bit (TOI) in timer interrupt mask register 2 (TMSK2).
Refer to 7.4.2 GPT Interrupts for more information.
All GPT input capture functions use the same 16-bit timer counter (TCNT). Each input
capture pin has a dedicated 16-bit latch and input edge-detection/selection logic. Each
input capture function has an associated status flag, and can cause the GPT to make
an interrupt service request.
When a selected edge transition occurs on an input capture pin, the associated 16-bit
latch captures the content of TCNT and sets the appropriate status flag. An interrupt
request can be generated when the transition is detected.
Edge-detection logic consists of control bits that enable edge detection and select a
transition to detect. The EDGxA and EDGxB bits in timer control register 2 (TCTL2)
determine whether the input capture functions detect rising edges only, falling edges
only, or both rising and falling edges. Clearing both bits disables the input capture
function. Input capture functions operate independently of each other and can capture
the same TCNT value if individual input edges are detected within the same timer
count cycle.
Input capture interrupt logic includes a status flag, which indicates that an edge has
been detected, and an interrupt enable bit. An input capture event sets the ICxF bit in
the timer interrupt flag register 1 (TFLG1) and causes the GPT to make an interrupt
request if the corresponding ICxI bit is set in the timer interrupt mask register 1
(TMSK1). If the ICxI bit cleared, software must poll the status flag to determine that an
event has occurred. Refer to 7.4 Polled and Interrupt-Driven Operation for more in-
formation.
Input capture events are generally asynchronous to the timer counter. Because of this,
input capture signals are conditioned by a synchronizer and digital filter. Events are
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