MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 54
MC68331CEH25
Manufacturer Part Number
MC68331CEH25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68331CEH25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Controller Family/series
68K
No. Of I/o's
18
Cpu Speed
25MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
2
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Data Ram Size
80 B
Interface Type
QSPI, SCI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
18
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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Price
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4
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
4-12
SYNCR Y field determines the count modulus for a modulo 64 down counter, causing
it to divide by a value of Y + 1. When W or Y values change, VCO frequency changes,
and there is a VCO relock delay. The SYNCR X bit controls a divide-by-two circuit that
is not in the synthesizer feedback loop. When X = 0 (reset state), the divider is en-
abled, and system clock frequency is one-fourth VCO frequency; setting X disables
the divider, doubling clock speed without changing VCO speed. There is no relock de-
lay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
The reset state of SYNCR ($3F00) produces a modulus-64 count.
For the device to perform correctly, system clock and VCO frequencies selected by
the W, X, and Y bits must be within the limits specified for the MCU. Do not use a com-
bination of bit values that selects either an operating frequency or a VCO frequency
greater than the maximum specified values in APPENDIX A ELECTRICAL CHARAC-
TERISTICS.
Table 4-7 shows clock control multipliers for all possible combinations of SYNCR bits.
Table 4-8 shows clock frequencies available with a 32.768-kHz reference and a max-
imum specified clock frequency of 20.97 MHz.
Modulus
000000
000001
000010
011111
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
Y
[W:X] = 00
Freescale Semiconductor, Inc.
F
For More Information On This Product,
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
SYSTEM
Table 4-7 Clock Control Multipliers
4
8
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
=
F
REFERENCE
[W:X] = 01
104
112
120
128
136
144
152
160
168
16
24
32
40
48
56
64
72
80
88
96
8
Prescalers
4 Y
+
1
[W:X] = 10
2
2W
112
128
144
160
176
192
208
224
240
256
272
288
304
320
336
16
32
48
64
80
96
+
X
USER’S MANUAL
[W:X] = 11
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
32
64
96
MC68331
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