MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 234
MC68331CEH25
Manufacturer Part Number
MC68331CEH25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68331CEH25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Controller Family/series
68K
No. Of I/o's
18
Cpu Speed
25MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
2
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Data Ram Size
80 B
Interface Type
QSPI, SCI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
18
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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D
FRZ[1:0] — Freeze Control
SUPV — Supervisor/Unrestricted
IARB — Interrupt Arbitration
D.4.2 QTEST — QSM Test Register
D.4.3 QILR — QSM Interrupt Level Register
ILQSPI — Interrupt Level for QSPI
ILSCI — Interrupt Level for SCI
D-26
15
0
0
valid, but writes to QSPI RAM or any register are guaranteed valid. STOP is set during
reset. The SCI receiver and transmitter must be disabled before STOP is set. To stop
the QSPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP.
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the
IMB is asserted. FREEZE is asserted whenever the CPU enters background mode.
FRZ0 is reserved for future use.
Each module that generates interrupts must have an IARB value. IARB values are
used to arbitrate between interrupt requests of the same priority.
Used for factory test only.
The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and
SCI interrupt requests. QIVR determines the value of the interrupt vector number the
QSM supplies when it responds to an interrupt acknowledge cycle. At reset, QIVR is
initialized to vector number $0F, the uninitialized interrupt vector number. To use in-
terrupt-driven serial communication, a user-defined vector number must be written to
QIVR.
When an interrupt request is made, ILQSPI value determines which of the interrupt re-
quest signals is asserted; when a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond. ILQS-
PI must have a value in the range $0 (lowest priority) to $7 (highest priority).
When an interrupt request is made, ILSCI value determines which of the interrupt re-
quest signals is asserted. When a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond. The
field must have a value in the range $0 (lowest priority) to $7 (highest priority).
If ILQSPI and ILSCI have the same nonzero value, and both submodules simulta-
neously request interrupt service, the QSPI has priority.
RESET:
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
0 = Supervisor access
1 = User access
QIVR — QSM Interrupt Vector Register
14
0
0
13
0
ILQSPI
0
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
10
0
Go to: www.freescale.com
REGISTER SUMMARY
ILSCI
0
8
0
7
0
0
0
0
INTV
1
USER’S MANUAL
1
$YFFC02
$YFFC04
$YFFC05
1
MC68331
0
1
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