MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 111

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68331
USER’S MANUAL
ANDI to CCR
ANDI to SR
Instruction
DIVS/DIVU
CMPM
ADDQ
BCHG
BGND
CMPA
ABCD
ADDA
ADDX
CMP2
BCLR
CHK2
BKPT
BSET
BTST
CMPI
ADDI
ANDI
DBcc
CMP
ADD
AND
CHK
ASR
BRA
BSR
CLR
ASL
Bcc
1
#<data>, <ea>
#<data>, <ea>
#<data>, <ea>
#<data>, CCR
#<data>, <ea>
#<data>, <ea>
#<data>, <ea>
#<data>, <ea>
#<data>, <ea>
(An) +, (An) +
#<data>, SR
#<data>, Dn
#<data>, Dn
(An), – (An)
(An), – (An)
Dn, <label>
Dn, <ea>
<ea>, Dn
<ea>, An
<ea>, Dn
Dn, <ea>
Dn, <ea>
Dn, <ea>
Dn, <ea>
Dn, <ea>
<ea>, Dn
<ea>, Rn
<ea>, Dn
<ea>, An
<ea>, Rn
<ea>, Dn
Dn, Dn–
Dn, Dn–
#<data>
Syntax
<label>
<label>
<label>
Dn, Dn
Dn, Dn
<ea>
<ea>
<ea>
none
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-1 Instruction Set Summary
32/16
Operand Size
CENTRAL PROCESSING UNIT
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
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16, 32
16, 32
16, 32
8, 32
8, 32
8, 32
8, 32
none
none
8, 32
8, 32
8, 32
8, 32
16
16
16
16
8
8
8
16: 16
background mode, else format/vector offset
Lower bound Rn Upper bound, CCR shows result
PC
If breakpoint cycle acknowledged, then execute
If Rn < lower bound or Rn > upper bound, then
Immediate data + Destination
Immediate data + Destination
Source
returned operation word, else trap as illegal
If Dn < 0 or Dn < (ea), then CHK exception
(Destination – Source), CCR shows results
(Destination – Source), CCR shows results
(Destination – Source), CCR shows results
SP – 4
Source + Destination + X
(Destination – Data), CCR shows results
If background mode enabled, then enter
If condition false, then Dn – 1
(<bit number> of destination
Source + Destination
Source + Destination
If condition true, then PC + d
Source · Destination
Destination / Source
Data · Destination
(<bit number> of destination
(<bit number> of destination
– (SSP); SR
(<bit number> of destination
if Dn
10
+ Destination
Source · CCR
0
1
SP; PC
(signed or unsigned)
Source · SR
(– 1), then PC + d
0
bit of destination
CHK exception
PC + d
bit of destination
bit of destination
instruction.
Operation
Destination
– (SSP); (vector)
10
(SP); PC + d
+ X
PC
Destination
Destination
CCR
SR
Destination
Destination
Destination
Destination
Destination
Destination
Destination
PC
Z
PC
Z;
Z;
PC;
Z
PC
– (SSP);
PC
5-11
5