MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 59

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.4 External Bus Interface
MC68331
USER’S MANUAL
The external bus interface (EBI) transfers information between the internal MCU bus
and external devices. Figure 4-7 shows a basic system with external memory and pe-
ripherals.
The external bus has 24 address lines and 16 data lines. The EBI provides dynamic
sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word
transfers. Ports are accessed through the use of asynchronous cycles controlled by
the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and
DSACK0). Multiple bus cycles may be required for a transfer to or from an 8-bit port.
The maximum number of bits transferred during an access is referred to as port width.
Widths of eight and sixteen bits can be accessed by asynchronous bus cycles con-
trolled by the data size (SIZ[1:0]) and the data and size acknowledge (DSACK[1:0])
signals. Multiple bus cycles may be required for a dynamically-sized transfer.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic
can be synchronized with EBI transfers. Refer to 4.8 Chip Selects for more informa-
tion.
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
Freescale Semiconductor, Inc.
ADDR[23:0]
DATA[15:0]
MCU
CSBOOT
For More Information On This Product,
CLKOUT
DSACK
Figure 4-7 MCU Basic System
CS3
R/W
CS5
FC
IRQ
SIZ
AS
DS
SYSTEM INTEGRATION MODULE
1
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DSACK
DS
DATA[15:0]
DATA[15:8]
R/W
DATA[7:0]
R/W
SIZ
CLK
AS
CS
IACK
IRQ
ADDR[15:0]
ADDR[23:0]
CS
ADDR[23:0]
CS
PERIPHERAL
ASYNC BUS
MEMORY
MEMORY
2
2
2
32 EXAMPLE SYS BLOCK
4-17
4