MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 136

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6
6.3.5 QSPI Operating Modes
6-10
The QSPI operates in either master or slave mode. Master mode is used when the
MCU originates data transfers. Slave mode is used when an external device initiates
serial transfers to the MCU through the QSPI. Switching between the modes is con-
trolled by MSTR in SPCR0. Before either mode is entered, appropriate QSM and QSPI
registers must be initialized properly.
In master mode, the QSPI executes a queue of commands defined by control bits in
each command RAM queue entry. Chip-select pins are activated, data is transmitted
from transmit RAM and received by the receive RAM.
In slave mode, operation proceeds in response to SS pin activation by an external bus
master. Operation is similar to master mode, but no peripheral chip selects are gener-
ated, and the number of bits transferred is controlled in a different manner. When the
QSPI is selected, it automatically executes the next queue transfer to exchange data
with the external device correctly.
Although the QSPI inherently supports multimaster operation no special arbitration
mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master
arbitration. System software must provide arbitration. Note that unlike previous SPI
systems, MSTR is not cleared by a mode fault being set nor are the QSPI pin output
drivers disabled. The QSPI and associated output drivers must be disabled by clearing
SPE in SPCR1.
Figure 6-4 shows QSPI initialization; Figure 6-5 and Figure 6-6 show QSPI master
and slave operation. The CPU must initialize the QSM global and pin registers and the
QSPI control registers before enabling the QSPI for either mode of operation (refer to
6.5 QSM Initialization). The command queue must be written before the QSPI is en-
abled for master mode operation. Any data to be transmitted should be written into
transmit RAM before the QSPI is enabled. During wraparound operation, data for sub-
sequent transmissions can be written at any time.
Freescale Semiconductor, Inc.
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USER’S MANUAL
MC68331