MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 116

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5
5.9.2 Types of Exceptions
5-16
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are ob-
tained from an external device; others are supplied by the processor. The processor
multiplies the vector number by four to calculate vector offset, then adds the offset to
the contents of the VBR. The sum is the memory address of the vector.
An exception can be caused by internal or external events.
An internal exception can be generated by an instruction or by an error. The TRAP,
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause excep-
tions during normal execution. Illegal instructions, instruction fetches from odd ad-
dresses, word or long-word operand accesses from odd addresses, and privilege
violations also cause internal exceptions.
Number
64–255
Vector
16–23
32–47
48–58
59–63
10
11
12
13
14
15
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
Table 5-2 Exception Vector Assignments
Freescale Semiconductor, Inc.
1020
Dec
100
104
108
112
116
120
124
128
188
192
232
236
252
256
12
16
20
24
28
32
36
40
44
48
52
56
60
64
92
96
For More Information On This Product,
0
4
8
Vector Offset
CENTRAL PROCESSING UNIT
0BC
0EC
0FC
3FC
Hex
00C
01C
02C
03C
05C
06C
07C
0C0
0E8
000
004
008
010
014
018
020
024
028
030
034
038
040
060
064
068
070
074
078
080
100
Go to: www.freescale.com
Space
SP
SP
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
(Reserved, Coprocessor Protocol Violation)
Format Error and Uninitialized Interrupt
Format Error and Uninitialized Interrupt
Trap Instruction Vectors (0–15)
Reset: Initial Program Counter
TRAPcc, TRAPV Instructions
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
User Defined Vectors (192)
Reset: Initial Stack Pointer
(Reserved, Coprocessor)
(Unassigned, Reserved)
(Unassigned, Reserved)
CHK, CHK2 Instructions
Hardware Breakpoint
Line 1010 Emulator
Line 1111 Emulator
Privilege Violation
Spurious Interrupt
Illegal Instruction
Address Error
Zero Division
Assignment
Bus Error
Trace
USER’S MANUAL
MC68331