MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 117

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.9.3 Exception Processing Sequence
5.10 Development Support
5.10.1 M68000 Family Development Support
MC68331
USER’S MANUAL
Sources of external exception include interrupts, breakpoints, bus errors, and reset re-
quests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access con-
trol and processor restart.
For all exceptions other than a reset exception, exception processing occurs in the fol-
lowing sequence. Refer to 4.6 Reset for details of reset processing.
As exception processing begins, the processor makes an internal copy of the status
register. After the copy is made, the processor state bits in the status register are
changed — the S bit is set, establishing supervisor access level, and bits T1 and T0
are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority
mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from
CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions,
internal logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and
placed on the supervisor stack. All stack frames contain copies of the status register
and the program counter for use by RTE. The type of exception and the context in
which the exception occurs determine what other information is stored in the stack
frame.
Finally, the processor prepares to resume normal execution of instructions. The ex-
ception vector offset is determined by multiplying the vector number by four, and the
offset is added to the contents of the VBR to determine displacement into the excep-
tion vector table. The exception vector is loaded into the program counter. If no other
exception is pending, the processor will resume normal execution at the new address
in the PC.
The following features have been implemented on the CPU32 to enhance the instru-
mentation and development environment:
All M68000 Family members include features to facilitate applications development.
These features include the following:
Trace on Instruction Execution — M68000 Family processors include an instruction-
• M68000 Family Development Support
• Background Debugging Mode
• Deterministic Opcode Tracking
• Hardware Breakpoints
by-instruction tracing facility as an aid to program development. The MC68020,
MC68030, MC68040, and CPU32 also allow tracing only of those instructions
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
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