MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 146

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6
6.3.5.3 Slave Mode
6-20
can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does not abort
a current request.
There are two recommended methods of exiting wraparound mode: clearing the
WREN bit or setting the HALT bit in SPCR3. Exiting wraparound mode by clearing
SPE is not recommended, as clearing SPE may abort a serial transfer in progress. The
QSPI sets SPIF, clears SPE, and stops the first time it reaches the end of the queue
after WREN is cleared. After HALT is set, the QSPI finishes the current transfer, then
stops executing commands. After the QSPI stops, SPE can be cleared.
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the
QSPI is unable to initiate serial transfers. Transfers are initiated by an external bus
master. Slave mode is typically used on a multi-master SPI bus. Only one device can
be bus master (operate in master mode) at any given time.
Before QSPI operation is initiated, QSM register PQSPAR must be written to assign
necessary pins to the QSPI. The pins necessary for slave mode operation are MISO
and MOSI, SCK, and PCS0/SS. MISO is used for serial data output in slave mode, and
MOSI is used for serial data input. Either or both may be necessary, depending on the
particular application. SCK is the serial clock input in slave mode. Assertion of the ac-
tive-low slave select signal (SS) initiates slave mode operation.
Before slave mode operation is initiated, DDRQS must be written to direct data flow
on the QSPI pins used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The
MISO pin must be configured as an output.
After pins are assigned and configured, write data to be transmitted into transmit RAM.
Command RAM is not used in slave mode and does not need to be initialized. Unused
portions of QSPI RAM can be used by the CPU as general-purpose RAM. Initialize the
queue pointers as appropriate.
When SPE is set and MSTR is clear, a low state on the slave select (PCS0/SS) pin
begins slave mode operation at the address indicated by NEWQP. Data that is re-
ceived is stored at the pointer address in receive RAM. Data is simultaneously loaded
into the data serializer from the pointer address in transmit RAM and transmitted.
Transfer is synchronized with the externally generated SCK. The CPHA and CPOL
bits determine on which SCK edge to latch incoming data from the MISO pin and to
drive outgoing data from the MOSI pin.
Because the command control segment is not used, the command control bits and pe-
ripheral chip-select codes have no effect in slave mode operation. The PCS0/SS pin
is used only as an input.
The SPBR, DT and DSCK bits are not used in slave mode. The QSPI drives neither
the clock nor the chip-select pins and thus cannot control clock rate or transfer delay.
Because the BITSE option is not available in slave mode, the BITS field specifies the
number of bits to be transferred for all transfers in the queue. When the number of bits
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MC68331